omnibus commit. hid stats. dac trait improvements. refactor to state machine style.

src/hw.rs

@@ -1,3 +1,6 @@
+use crate::pac;
+use defmt::debug;
+
 pub(crate) struct PllConstants {
     pub m: u16,   // 1-65535
     pub n: u8,    // 1-255
@@ -54,3 +57,58 @@ impl defmt::Format for PllConstants {
         );
     }
 }
+
+const SYS_PLL: PllConstants = PllConstants::new(4, 75, 1); // 150MHz
+
+pub(crate) fn init_sys_pll1() {
+    let syscon = unsafe { &*pac::SYSCON::ptr() };
+    let pmc = unsafe { &*pac::PMC::ptr() };
+    let anactrl = unsafe { &*pac::ANACTRL::ptr() };
+
+    debug!("start clk_in");
+    pmc.pdruncfg0
+        .modify(|_, w| w.pden_xtal32m().poweredon().pden_ldoxo32m().poweredon());
+    syscon.clock_ctrl.modify(|_, w| w.clkin_ena().enable());
+    anactrl
+        .xo32m_ctrl
+        .modify(|_, w| w.enable_system_clk_out().enable());
+
+    debug!("init pll1: {}", SYS_PLL);
+    pmc.pdruncfg0.modify(|_, w| w.pden_pll1().poweredoff());
+    syscon.pll1clksel.write(|w| w.sel().enum_0x1()); // clk_in
+    syscon.pll1ctrl.write(|w| unsafe {
+        w.clken()
+            .enable()
+            .seli()
+            .bits(SYS_PLL.seli)
+            .selp()
+            .bits(SYS_PLL.selp)
+    });
+
+    syscon
+        .pll1ndec
+        .write(|w| unsafe { w.ndiv().bits(SYS_PLL.n) });
+    syscon.pll1ndec.write(|w| unsafe {
+        w.ndiv().bits(SYS_PLL.n).nreq().set_bit() // latch
+    });
+    syscon
+        .pll1mdec
+        .write(|w| unsafe { w.mdiv().bits(SYS_PLL.m) });
+    syscon
+        .pll1pdec
+        .write(|w| unsafe { w.pdiv().bits(SYS_PLL.p) });
+    syscon.pll1pdec.write(|w| unsafe {
+        w.pdiv().bits(SYS_PLL.p).preq().set_bit() // latch
+    });
+
+    pmc.pdruncfg0.modify(|_, w| w.pden_pll1().poweredon());
+    debug!("pll1 wait for lock");
+    let mut i = 0usize;
+    while syscon.pll1stat.read().lock().bit_is_clear() {
+        i += 1;
+    }
+    debug!("pll1 locked after {} tries", i);
+    // switch system clock to pll1
+    syscon.fmccr.modify(|_, w| w.flashtim().flashtim11());
+    syscon.mainclkselb.modify(|_, w| w.sel().enum_0x2()); // pll1
+}