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version = "1.0.0", features = ["print-defmt"] } +static_cell = "2.1.1" +usb-device = "0.3" +usbd-uac2 = { version = "0.1.0", path = "../usbd_uac2", features = ["defmt"]} + +[profile.release] +opt-level = "z" +lto = true +debug = true +codegen-units = 1 diff --git a/memory.x b/memory.x new file mode 100644 index 0000000..5a68a5f --- /dev/null +++ b/memory.x @@ -0,0 +1,21 @@ +MEMORY +{ + FLASH : ORIGIN = 0x00000000, LENGTH = 512K + + /* for use with standard link.x */ + RAM : ORIGIN = 0x20000000, LENGTH = 192K + + /* would be used with proper link.x */ + /* needs changes to r0 (initialization code) */ + /* SRAM0 : ORIGIN = 0x20000000, LENGTH = 64K */ + /* SRAM1 : ORIGIN = 0x20010000, LENGTH = 64K */ + /* SRAM2 : ORIGIN = 0x20020000, LENGTH = 64K */ + /* SRAM3 : ORIGIN = 0x20030000, LENGTH = 64K */ + + /* CASPER SRAM regions */ + /* SRAMX0: ORIGIN = 0x1400_0000, LENGTH = 4K /1* to 0x1400_0FFF *1/ */ + /* SRAMX1: ORIGIN = 0x1400_4000, LENGTH = 4K /1* to 0x1400_4FFF *1/ */ + + /* USB1 SRAM regin */ + /* USB1_SRAM : ORIGIN = 0x40100000, LENGTH = 16K */ +} diff --git a/src/ak4490.rs b/src/ak4490.rs new file mode 100644 index 0000000..8139cca --- /dev/null +++ b/src/ak4490.rs @@ -0,0 +1,48 @@ +use cortex_m::prelude::{_embedded_hal_blocking_i2c_Write, _embedded_hal_blocking_i2c_WriteRead}; +use defmt::warn; + +use crate::hal::prelude::*; +use crate::{CodecPins, MCLK_FREQ, SAMPLE_RATE, SampleType}; + +const AK4490_I2C_ADDRESS: u8 = 0x10; + +#[repr(u8)] +enum RegisterAddress { + Control1 = 0x00, + Control2 = 0x01, + Control3 = 0x02, + LeftAtt = 0x03, + RightAtt = 0x04, + Control4 = 0x05, + Control5 = 0x06, + Control6 = 0x07, + Control7 = 0x08, + Control8 = 0x09, +} + +#[inline] +fn write_reg(i2c: &mut T, reg: RegisterAddress, val: u8) +where + T: _embedded_hal_blocking_i2c_WriteRead + _embedded_hal_blocking_i2c_Write, +{ + i2c.write(AK4490_I2C_ADDRESS, &[reg as u8, val]).ok(); +} + +pub(crate) fn init_dac(i2c: &mut T, mut pins: CodecPins) +where + T: _embedded_hal_blocking_i2c_WriteRead + _embedded_hal_blocking_i2c_Write, +{ + // bring out of reset + pins.reset.set_high(); + write_reg(i2c, RegisterAddress::Control1, (1 << 7) | 0x0e | (1 << 0)); // ACKS | I2S-32 | RSTN + let dfs = match SAMPLE_RATE { + r if r < 54000 => 0, + r if r < 108000 => 1, + r if r < 216000 => 2, + r if r <= 384000 => 4, + _ => 5, + }; + // default = 0x22 + write_reg(i2c, RegisterAddress::Control2, 0x22 | ((dfs & 0x3) << 3)); + write_reg(i2c, RegisterAddress::Control4, (dfs & 0x4) >> 1); +} diff --git a/src/hw.rs b/src/hw.rs new file mode 100644 index 0000000..656acf9 --- /dev/null +++ b/src/hw.rs @@ -0,0 +1,56 @@ +pub(crate) struct PllConstants { + pub m: u16, // 1-65535 + pub n: u8, // 1-255 + pub p: u8, // 1-31 + pub selp: u8, // 5 bits + pub seli: u8, // 6 bits +} + +impl PllConstants { + pub(crate) const fn new(n: u8, m: u16, p: u8) -> Self { + assert!(n != 0, "1 <= N <= 255"); + assert!(m != 0, "1 <= M <= 65535"); + assert!(p != 0 && p <= 31, "1 <= P <= 31"); + + // Following ripped from lpc55-hal and made const + // UM 4.6.6.3.2 + let selp = { + let v = (m >> 2) + 1; + if v < 31 { v } else { 31 } + } as u8; + + let seli = { + let v = match m { + m if m >= 8000 => 1, + m if m >= 122 => 8000 / m, + _ => 2 * (m >> 2) + 3, + }; + + if v < 63 { v } else { 63 } + } as u8; + // let seli = min(2*(m >> 2) + 3, 63); + Self { + n, + m, + p, + selp, + seli, + } + } +} +impl defmt::Format for PllConstants { + fn format(&self, fmt: defmt::Formatter) { + let factor = f32::from(self.m) / (f32::from(self.n) * 2.0 * f32::from(self.p)); + + defmt::write!( + fmt, + "m: {} n: {} p: {} selp: {} seli: {} fout: fin * {}", + self.m, + self.n, + self.p, + self.selp, + self.seli, + factor + ); + } +} diff --git a/src/main.rs b/src/main.rs new file mode 100644 index 0000000..7a5e2bf --- /dev/null +++ b/src/main.rs @@ -0,0 +1,543 @@ +#![no_main] +#![no_std] + +extern crate panic_probe; +#[defmt::panic_handler] +fn panic() -> ! { + panic_probe::hard_fault() +} + +use core::ptr::null_mut; +use core::sync::atomic::{AtomicBool, AtomicI32, AtomicUsize, Ordering}; +use cortex_m_rt::entry; +use defmt; +use defmt::debug; +use defmt_rtt as _; +use hal::Pin; +use hal::Syscon; +use hal::drivers::{Timer, UsbBus, pins, pins::direction::Output}; +use hal::prelude::*; +use hal::raw as pac; +use hal::time::Hertz; +use hal::typestates::pin::state::Gpio; +use heapless::spsc::Consumer; +use lpc55_hal::{self as hal}; +use pac::interrupt; +use static_cell::StaticCell; +use usb_device::{ + bus::{self}, + device::{StringDescriptors, UsbDeviceBuilder, UsbVidPid}, + endpoint::IsochronousSynchronizationType, +}; +use usbd_uac2::UsbIsochronousFeedback; +use usbd_uac2::{ + self, AudioClassConfig, RangeEntry, TerminalConfig, UsbAudioClass, UsbAudioClockImpl, UsbSpeed, + constants::{FunctionCode, TerminalType}, + descriptors::{ChannelConfig, ClockType, FormatType1, LockDelay}, +}; + +#[cfg(feature = "ak4490")] +mod ak4490; +#[cfg(feature = "ak4490")] +use ak4490 as dac; +mod hw; + +// Fo = M/(N*2*P) * Fin +// Fo = 3072/(125*2*8) * 16MHz = 24.576MHz +const FIFO_LENGTH: usize = 128; // frames +const MCLK_FREQ: u32 = 24576000; +const SAMPLE_RATE: u32 = 48000; +type SampleType = (i32, i32); + +struct CodecPins { + reset: Pin>, +} + +struct ClockSelPins { + sel_24m: Pin>, + sel_22m: Pin>, +} + +struct Clock { + pins: ClockSelPins, + cur_rate: u32, +} +impl Clock { + const RATES: [RangeEntry; 1] = [RangeEntry::new_fixed(SAMPLE_RATE)]; +} +impl UsbAudioClockImpl for Clock { + const CLOCK_TYPE: usbd_uac2::descriptors::ClockType = ClockType::InternalFixed; + const SOF_SYNC: bool = false; + fn get_sample_rate(&self) -> core::result::Result { + Ok(self.cur_rate) + } + fn set_sample_rate( + &mut self, + sample_rate: u32, + ) -> core::result::Result<(), usbd_uac2::UsbAudioClassError> { + if 24_576_000u32.is_multiple_of(sample_rate) { + defmt::info!("[clock] 24M clock selected"); + self.pins.sel_22m.set_low().ok(); + // hal::wait_at_least(1); + self.pins.sel_24m.set_high().ok(); + } else { + defmt::info!("[clock] 24M clock selected"); + self.pins.sel_24m.set_low().ok(); + // hal::wait_at_least(1); + self.pins.sel_22m.set_high().ok(); + }; + self.cur_rate = sample_rate; + Ok(()) + } + fn get_rates( + &self, + ) -> core::result::Result<&[usbd_uac2::RangeEntry], usbd_uac2::UsbAudioClassError> { + Ok(&Clock::RATES) + } + fn get_clock_validity(&self) -> core::result::Result { + Ok(true) + } + fn alt_setting( + &mut self, + alt_setting: u8, + ) -> core::result::Result<(), usbd_uac2::UsbAudioClassError> { + match alt_setting { + 0 => { + self.pins.sel_22m.set_low().ok(); + self.pins.sel_24m.set_low().ok(); + } + 1 => { + self.set_sample_rate(self.cur_rate).ok(); + } + _ => {} + }; + Ok(()) + } +} + +#[derive(Default)] +struct PerfCounters { + received_frames: AtomicUsize, + played_frames: AtomicUsize, + min_fill: AtomicUsize, + avg_fill: AtomicUsize, + queue_underflows: AtomicUsize, + queue_overflows: AtomicUsize, + audio_underflows: AtomicUsize, +} + +impl PerfCounters { + fn reset(&self) { + self.received_frames.store(0, Ordering::Relaxed); + self.played_frames.store(0, Ordering::Relaxed); + self.min_fill.store(FIFO_LENGTH, Ordering::Relaxed); + self.avg_fill.store(FIFO_LENGTH / 2, Ordering::Relaxed); + self.queue_underflows.store(0, Ordering::Relaxed); + self.queue_overflows.store(0, Ordering::Relaxed); + self.audio_underflows.store(0, Ordering::Relaxed); + } +} + +impl defmt::Format for PerfCounters { + fn format(&self, fmt: defmt::Formatter) { + defmt::write!( + fmt, + "frames: {}/{} min_fill: {} avg fill: {} a_underflows: {} q_underflows: {} q_overflows: {}", + self.played_frames.load(Ordering::Relaxed), + self.received_frames.load(Ordering::Relaxed), + self.min_fill.load(Ordering::Relaxed), + self.avg_fill.load(Ordering::Relaxed), + self.audio_underflows.load(Ordering::Relaxed), + self.queue_underflows.load(Ordering::Relaxed), + self.queue_overflows.load(Ordering::Relaxed) + ) + } +} + +static FIFO_CONSUMER_STORE: StaticCell> = StaticCell::new(); +static mut FIFO_CONSUMER: *mut Consumer = null_mut(); + +static PERF: PerfCounters = PerfCounters { + received_frames: AtomicUsize::new(0), + played_frames: AtomicUsize::new(0), + min_fill: AtomicUsize::new(FIFO_LENGTH), + avg_fill: AtomicUsize::new(FIFO_LENGTH / 2), + queue_underflows: AtomicUsize::new(0), + queue_overflows: AtomicUsize::new(0), + audio_underflows: AtomicUsize::new(0), +}; + +#[interrupt] +fn FLEXCOMM7() { + let i2s = unsafe { &*pac::I2S7::ptr() }; + + if i2s.fifostat.read().txlvl().bits() == 0 { + PERF.audio_underflows.fetch_add(1, Ordering::Relaxed); + } + + // refil the buffer to 4 frames / 8 samples + let fifo = unsafe { &mut *FIFO_CONSUMER }; + while i2s.fifostat.read().txlvl().bits() <= 6 { + if let Some((l, r)) = fifo.dequeue() { + i2s.fifowr.write(|w| unsafe { w.bits(l as u32) }); + i2s.fifowr.write(|w| unsafe { w.bits(r as u32) }); + PERF.min_fill.fetch_min(fifo.len(), Ordering::Relaxed); + PERF.played_frames.fetch_add(1, Ordering::Relaxed); + } else { + PERF.queue_underflows.fetch_add(1, Ordering::Relaxed); + i2s.fifowr.write(|w| unsafe { w.bits(0) }); + i2s.fifowr.write(|w| unsafe { w.bits(0) }); + } + } +} + +struct Audio<'a> { + running: AtomicBool, + i2s: I2sTx, + producer: heapless::spsc::Producer<'a, SampleType>, + integrator: AtomicI32, +} +impl<'a> Audio<'a> { + fn start(&self) { + self.running.store(true, Ordering::Relaxed); + defmt::info!("playback starting, enabling interrupts"); + self.i2s.i2s.fifointenclr.write(|w| w.txlvl().set_bit()); + // FIFO threshold trigger enable + self.i2s + .i2s + .fifotrig + .modify(|_, w| unsafe { w.txlvl().bits(6).txlvlena().enabled() }); + // FIFO level interrupt enable + self.i2s.i2s.fifointenset.modify(|_, w| w.txlvl().enabled()); + unsafe { pac::NVIC::unmask(pac::Interrupt::FLEXCOMM7) }; + } + fn stop(&self) { + self.running.store(true, Ordering::Relaxed); + defmt::info!("playback stopped: {}", PERF); + PERF.reset(); + pac::NVIC::mask(pac::Interrupt::FLEXCOMM7); + } +} +impl<'a, B: bus::UsbBus> UsbAudioClass<'a, B> for Audio<'_> { + fn alternate_setting_changed(&mut self, terminal: usb_device::UsbDirection, alt_setting: u8) { + match alt_setting { + 0 => self.stop(), + 1 => self.start(), + _ => defmt::error!("unexpected alt setting {}", alt_setting), + } + } + fn audio_data_rx( + &mut self, + ep: &usb_device::endpoint::Endpoint<'a, B, usb_device::endpoint::Out>, + ) { + let mut buf = [0; SAMPLE_RATE as usize / 1000 * 64]; + let len = match ep.read(&mut buf) { + Ok(len) => len, + Err(e) => { + defmt::error!("usb error in rx callback"); + return; + } + }; + let buf = &buf[..len]; + for sample in buf.chunks_exact(8).map(|b| { + PERF.received_frames.fetch_add(1, Ordering::Relaxed); + ( + i32::from_le_bytes(b[..4].try_into().unwrap()), + i32::from_le_bytes(b[4..].try_into().unwrap()), + ) + }) { + if let Err(e) = self.producer.enqueue(sample) { + PERF.queue_overflows.fetch_add(1, Ordering::Relaxed); + // defmt::error!("overflowed fifo, len: {}", unsafe { + // (*self.producer.get()).len() + // }); + } + } + } + fn feedback(&mut self) -> Option { + const TARGET: i32 = FIFO_LENGTH as i32 / 2 - 64; + const NOMINAL: i32 = (SAMPLE_RATE as i32 / 1000) << 16; + + let queuelen = self.producer.len(); + let error = (queuelen as i32 - TARGET).clamp(-32, 32); + + // --- integrator --- + let scaled_error = error / 64; + + let new_i = self.integrator.fetch_add(scaled_error, Ordering::Relaxed) + scaled_error; + let clamped = new_i.clamp(-131072, 131072); + + // leak + store final value + let leaked = clamped - (clamped >> 8); + self.integrator.store(leaked, Ordering::Relaxed); + + // reset on large deviation + if error.abs() > 96 { + self.integrator.store(0, Ordering::Relaxed); + } + + // --- gains --- + let p = error / 128; + let i = leaked / 32768; + + // correction + let correction = (-(p + i)).clamp(-32, 32); + let v = NOMINAL + (correction << 10); + + // EMA (unchanged, already correct) + let ema = PERF.avg_fill.load(Ordering::Relaxed); + let new = ((ema * 1023) + queuelen + 512) >> 10; + PERF.avg_fill.store(new, Ordering::Relaxed); + + defmt::debug!( + "q:{} p:{} i:{} err:{} fb:{}+{}", + queuelen, + p, + i, + error, + NOMINAL >> 16, + correction + ); + + Some(UsbIsochronousFeedback::new(v as u32)) + } +} + +pub struct I2sTx { + pub i2s: pac::I2S7, +} + +pub fn init_i2s(mut fc7: pac::FLEXCOMM7, i2s7: pac::I2S7, syscon: &mut Syscon) -> I2sTx { + defmt::debug!("init i2s"); + // Enable BOTH + syscon.reset(&mut fc7); + syscon.enable_clock(&mut fc7); + + unsafe { + pac::IOCON::ptr().as_ref().unwrap().pio0_23.modify(|_, w| { + w.func() + .alt1() // MCLK + .mode() + .inactive() + .slew() + .fast() + .invert() + .disabled() + .digimode() + .digital() + .od() + .normal() + }); + pac::SYSCON::ptr() + .as_ref() + .unwrap() + .mclkio + .modify(|_, w| w.mclkio().input()); + pac::SYSCON::ptr() + .as_ref() + .unwrap() + .fcclksel7() + .modify(|_, w| w.sel().enum_0x5()); // MCLK + }; + + // Select I2S TX function + fc7.pselid.write(|w| w.persel().i2s_transmit()); + + let regs = i2s7; + + // Enable TX FIFO only + regs.fifocfg.modify(|_, w| { + w.enabletx() + .enabled() + .enablerx() + .disabled() + .dmatx() + .disabled() + .txi2se0() + .zero() + }); + + // Flush + regs.fifocfg.modify(|_, w| w.emptytx().set_bit()); + + regs.cfg2 + .modify(|_, w| unsafe { w.position().bits(0).framelen().bits(63) }); // framelen = 64 + + let bclk_div = (MCLK_FREQ / SAMPLE_RATE / 64) as u16; + regs.div + .modify(|_, w| unsafe { w.div().bits(bclk_div - 1) }); // Clock source is MCLK (12.288MHz) / 4 = 3MHz + + // Config + regs.cfg1.modify(|_, w| unsafe { + w.mstslvcfg() + .normal_master() + .onechannel() + .dual_channel() + .datalen() + .bits(31) + .mainenable() + .enabled() + .mode() + .classic_mode() + .datapause() + .normal() + }); + + I2sTx { i2s: regs } +} + +#[entry] +fn main() -> ! { + let hal = hal::new(); + + let mut anactrl = hal.anactrl; + let mut pmc = hal.pmc; + let mut syscon = hal.syscon; + + let mut gpio = hal.gpio.enabled(&mut syscon); + let mut iocon = hal.iocon.enabled(&mut syscon); + + debug!("start"); + + debug!("iocon"); + let usb0_vbus_pin = pins::Pio0_22::take() + .unwrap() + .into_usb0_vbus_pin(&mut iocon); + let codec_i2c_pins = ( + pins::Pio0_16::take().unwrap().into_i2c4_scl_pin(&mut iocon), + pins::Pio0_5::take().unwrap().into_i2c4_sda_pin(&mut iocon), + ); + let codec_i2s_pins = ( + pins::Pio0_21::take().unwrap().into_spi7_sck_pin(&mut iocon), + pins::Pio0_20::take().unwrap().into_i2s7_sda_pin(&mut iocon), + pins::Pio0_19::take().unwrap().into_i2s7_ws_pin(&mut iocon), + pins::Pio0_23::take().unwrap(), + ); + let codec_gpio_pins = CodecPins { + reset: pins::Pio0_3::take() + .unwrap() + .into_gpio_pin(&mut iocon, &mut gpio) + .into_output_low(), + }; + let clock_sel_pins = ClockSelPins { + sel_24m: pins::Pio0_27::take() + .unwrap() + .into_gpio_pin(&mut iocon, &mut gpio) + .into_output_low(), + sel_22m: pins::Pio0_31::take() + .unwrap() + .into_gpio_pin(&mut iocon, &mut gpio) + .into_output_low(), + }; + let leds = ( + pins::Pio0_13::take() + .unwrap() + .into_gpio_pin(&mut iocon, &mut gpio) + .into_output_low(), + pins::Pio0_14::take() + .unwrap() + .into_gpio_pin(&mut iocon, &mut gpio) + .into_output_low(), + ); + + // iocon.disabled(&mut syscon).release(); // save the environment :) + + debug!("clocks"); + let clocks = hal::ClockRequirements::default() + .system_frequency(96.MHz()) + .configure(&mut anactrl, &mut pmc, &mut syscon) + .unwrap(); + let mut _delay_timer = Timer::new( + hal.ctimer + .0 + .enabled(&mut syscon, clocks.support_1mhz_fro_token().unwrap()), + ); + + debug!("peripherals"); + + let i2c_peripheral = hal + .flexcomm + .4 + .enabled_as_i2c(&mut syscon, &clocks.support_flexcomm_token().unwrap()); + let mut i2c_bus = I2cMaster::new( + i2c_peripheral, + codec_i2c_pins, + Hertz::try_from(400.kHz()).unwrap(), + ); + + let i2s_peripheral = { + let fc7 = hal.flexcomm.7.release(); + init_i2s(fc7.0, fc7.2, &mut syscon) + }; + + let usb_peripheral = hal.usbhs.enabled_as_device( + &mut anactrl, + &mut pmc, + &mut syscon, + &mut _delay_timer, + clocks.support_usbhs_token().unwrap(), + ); + + let usb_bus = UsbBus::new(usb_peripheral, usb0_vbus_pin); + let mut clock = Clock { + pins: clock_sel_pins, + cur_rate: SAMPLE_RATE, + }; + + defmt::debug!("codec init"); + dac::init_dac(&mut i2c_bus, codec_gpio_pins); + let queue = cortex_m::singleton!( + : heapless::spsc::Queue + = heapless::spsc::Queue::new() + ) + .unwrap(); + let (producer, consumer) = queue.split(); + + let consumer_ref = FIFO_CONSUMER_STORE.init(consumer); + unsafe { FIFO_CONSUMER = consumer_ref as *mut _ }; + + let mut audio = Audio { + i2s: i2s_peripheral, + producer, + running: AtomicBool::new(false), + integrator: AtomicI32::new(0), + }; + + let config = AudioClassConfig::new(UsbSpeed::High, FunctionCode::Other, &mut clock, &mut audio) + .with_output_config(TerminalConfig::new( + 2, + 1, + 2, + FormatType1 { + bit_resolution: 32, + bytes_per_sample: 4, + }, + TerminalType::ExtLineConnector, + ChannelConfig::default_chans(2), + IsochronousSynchronizationType::Asynchronous, + LockDelay::Undefined(0), + None, + )); + + let mut uac2 = config.build(&usb_bus).unwrap(); + + let mut usb_dev = UsbDeviceBuilder::new(&usb_bus, UsbVidPid(0x1209, 0xcc1d)) + .composite_with_iads() + .strings(&[StringDescriptors::default() + .manufacturer("VE7XEN") + .product("Guac Tortilla") + .serial_number("123456789")]) + .unwrap() + .max_packet_size_0(64) + .unwrap() + .device_class(0xef) + .device_sub_class(0x02) + .device_protocol(0x01) + .build(); + + defmt::info!("main loop"); + + loop { + usb_dev.poll(&mut [&mut uac2]); + } +}