evk implementation for debugging, works except no audio output for some reason
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@@ -1,5 +1,5 @@
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use crate::pac;
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use defmt::debug;
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use defmt::{debug, info};
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pub(crate) struct PllConstants {
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pub m: u16, // 1-65535
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@@ -112,3 +112,75 @@ pub(crate) fn init_sys_pll1() {
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syscon.fmccr.modify(|_, w| w.flashtim().flashtim11());
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syscon.mainclkselb.modify(|_, w| w.sel().enum_0x2()); // pll1
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}
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// Fo = M/(N*2*P) * Fin
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// Fo = 3072/(125*2*8) * 16MHz = 24.576MHz
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const AUDIO_PLL: PllConstants = PllConstants::new(125, 3072, 8);
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// Set PLL0 to 24.576MHz, start, and wait for lock
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// This is not exposed by lpc55-hal, unfortunately. Copy their implementation here.
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pub(crate) fn init_audio_pll() {
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let syscon = unsafe { &*pac::SYSCON::ptr() };
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let pmc = unsafe { &*pac::PMC::ptr() };
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let anactrl = unsafe { &*pac::ANACTRL::ptr() };
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debug!("start clk_in");
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pmc.pdruncfg0
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.modify(|_, w| w.pden_xtal32m().poweredon().pden_ldoxo32m().poweredon());
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syscon.clock_ctrl.modify(|_, w| w.clkin_ena().enable());
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anactrl
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.xo32m_ctrl
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.modify(|_, w| w.enable_system_clk_out().enable());
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debug!("init pll0: {}", AUDIO_PLL);
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pmc.pdruncfg0
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.modify(|_, w| w.pden_pll0().poweredoff().pden_pll0_sscg().poweredoff());
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syscon.pll0clksel.write(|w| w.sel().enum_0x1()); // clk_in
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syscon.pll0ctrl.write(|w| unsafe {
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w.clken()
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.enable()
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.seli()
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.bits(AUDIO_PLL.seli)
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.selp()
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.bits(AUDIO_PLL.selp)
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});
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syscon
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.pll0ndec
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.write(|w| unsafe { w.ndiv().bits(AUDIO_PLL.n) });
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syscon.pll0ndec.write(|w| unsafe {
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w.ndiv().bits(AUDIO_PLL.n).nreq().set_bit() // latch
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});
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syscon
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.pll0pdec
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.write(|w| unsafe { w.pdiv().bits(AUDIO_PLL.p) });
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syscon.pll0pdec.write(|w| unsafe {
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w.pdiv().bits(AUDIO_PLL.p).preq().set_bit() // latch
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});
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syscon.pll0sscg0.write(|w| unsafe { w.md_lbs().bits(0) });
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syscon
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.pll0sscg1
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.write(|w| unsafe { w.mdiv_ext().bits(AUDIO_PLL.m).sel_ext().set_bit() });
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syscon.pll0sscg1.write(|w| unsafe {
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w.mdiv_ext()
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.bits(AUDIO_PLL.m)
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.sel_ext()
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.set_bit()
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.mreq()
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.set_bit() // latch
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.md_req()
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.set_bit() // latch
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});
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pmc.pdruncfg0
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.modify(|_, w| w.pden_pll0().poweredon().pden_pll0_sscg().poweredon());
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info!("pll0 wait for lock");
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let mut i = 0usize;
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while syscon.pll0stat.read().lock().bit_is_clear() {
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i += 1;
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}
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info!("pll0 locked after {} loops", i);
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}
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