use cortex_m::prelude::{_embedded_hal_blocking_i2c_Write, _embedded_hal_blocking_i2c_WriteRead};
use defmt::warn;

use crate::hal::prelude::*;
use crate::{CodecPins, MCLK_FREQ, SAMPLE_RATE, SampleType};

const AK4490_I2C_ADDRESS: u8 = 0x10;

#[repr(u8)]
enum RegisterAddress {
    Control1 = 0x00,
    Control2 = 0x01,
    Control3 = 0x02,
    LeftAtt = 0x03,
    RightAtt = 0x04,
    Control4 = 0x05,
    Control5 = 0x06,
    Control6 = 0x07,
    Control7 = 0x08,
    Control8 = 0x09,
}

#[inline]
fn write_reg<T>(i2c: &mut T, reg: RegisterAddress, val: u8)
where
    T: _embedded_hal_blocking_i2c_WriteRead + _embedded_hal_blocking_i2c_Write,
{
    i2c.write(AK4490_I2C_ADDRESS, &[reg as u8, val]).ok();
}

pub(crate) fn init_dac<T>(i2c: &mut T, mut pins: CodecPins)
where
    T: _embedded_hal_blocking_i2c_WriteRead + _embedded_hal_blocking_i2c_Write,
{
    // bring out of reset
    pins.reset.set_high();
    write_reg(i2c, RegisterAddress::Control1, (1 << 7) | 0x0e | (1 << 0)); // ACKS | I2S-32 | RSTN
    let dfs = match SAMPLE_RATE {
        r if r < 54000 => 0,
        r if r < 108000 => 1,
        r if r < 216000 => 2,
        r if r <= 384000 => 4,
        _ => 5,
    };
    // default = 0x22
    write_reg(i2c, RegisterAddress::Control2, 0x22 | ((dfs & 0x3) << 3));
    write_reg(i2c, RegisterAddress::Control4, (dfs & 0x4) >> 1);
}