examples: add dma example for lpc55s28-evk
This commit is contained in:
@@ -0,0 +1,403 @@
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use hal::Syscon;
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use hal::peripherals::syscon::ClockControl;
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use crate::{hal, pac};
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use core::cell::UnsafeCell;
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use core::convert::Infallible;
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use core::ptr::copy_nonoverlapping;
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use core::sync::atomic::{AtomicUsize, Ordering, compiler_fence};
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pub const DMA0_FLEXCOMM7_TX: u8 = 19;
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#[repr(C)]
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#[derive(Copy, Clone)]
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pub struct DmaDescriptor {
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pub xfercfg: u32,
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pub src_end: *const u8,
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pub dst_end: *mut u32,
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pub next: *const DmaDescriptor,
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}
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impl defmt::Format for DmaDescriptor {
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fn format(&self, fmt: defmt::Formatter) {
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defmt::write!(
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fmt,
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"xfercfg={:x} src_end={:x} dst_end={:x} next={:x}",
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self.xfercfg,
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self.src_end,
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self.dst_end,
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self.next
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)
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}
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}
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// Channel descriptor table; linked from SRAMBASE
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#[repr(C, align(512))]
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pub struct DescriptorTable {
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pub d: [DmaDescriptor; 32],
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}
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// Our ring that we will transition to once the transfer begins
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#[repr(C)]
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pub struct RingDescriptors<const N: usize> {
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pub d: [DmaDescriptor; N],
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}
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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pub struct PushResult {
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pub written: usize,
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pub dropped: usize,
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}
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#[derive(Debug, Copy, Clone, Eq, PartialEq)]
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pub enum ConfigError {
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SlotTooLarge,
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SlotTooSmall,
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SlotNotAligned,
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UnsupportedWidth,
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}
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#[derive(Debug)]
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pub enum DmaError {
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Underrun,
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}
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impl core::error::Error for DmaError {}
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impl core::fmt::Display for DmaError {
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fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
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f.write_str("DmaUnderrun")
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}
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}
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/// Slot-based DMA ring
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pub struct DmaRing<const N: usize, const MAX_SLOT_BYTES: usize> {
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dma: pac::DMA0,
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/// Destination peripheral register (FIFO write register)
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dst_reg: *mut u32,
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// SAFETY: only written by USB task (on start)
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pub(crate) channel_desc: UnsafeCell<DescriptorTable>,
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// SAFETY: only written by USB task (on start)
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pub(crate) desc: UnsafeCell<RingDescriptors<N>>,
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slots: UnsafeCell<[[u8; MAX_SLOT_BYTES]; N]>,
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/// Effective bytes per slot. Maybe be smaller than MAX_SLOT_BYTES (e.g. at lower sample rates), as the setup is designed for constant rate not constant size.
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slot_bytes: usize,
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/// How many bytes to transfer to the FIFO
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word_bytes: usize,
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// SAFETY: producer only
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write_slot: UnsafeCell<usize>,
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write_off: UnsafeCell<usize>,
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produced: AtomicUsize,
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consumed: AtomicUsize,
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/// Leave at least one slot empty so producer never overwrites a slot DMA may still read.
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safety_gap: usize,
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pub produced_bytes: AtomicUsize,
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pub consumed_bytes: AtomicUsize,
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}
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impl<const N: usize, const MAX_SLOT_BYTES: usize> DmaRing<N, MAX_SLOT_BYTES> {
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/// Construct using PAC DMA0 + &mut SYSCON + a destination FIFO register.
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pub fn new(
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dma: pac::DMA0,
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syscon: &mut Syscon,
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dst_reg: *mut u32,
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word_bytes: usize,
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) -> Result<Self, ConfigError> {
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if word_bytes != 1 && word_bytes != 2 && word_bytes != 4 {
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return Err(ConfigError::UnsupportedWidth);
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}
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// Start the DMA0 clock
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dma.enable_clock(syscon);
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Ok(Self {
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dma,
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dst_reg: dst_reg,
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channel_desc: UnsafeCell::new(DescriptorTable {
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d: [DmaDescriptor {
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xfercfg: 0,
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src_end: core::ptr::null(),
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dst_end: core::ptr::null_mut(),
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next: core::ptr::null(),
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}; 32],
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}),
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desc: UnsafeCell::new(RingDescriptors {
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d: [DmaDescriptor {
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xfercfg: 0,
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src_end: core::ptr::null(),
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dst_end: core::ptr::null_mut(),
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next: core::ptr::null(),
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}; N],
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}),
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slots: UnsafeCell::new([[0u8; MAX_SLOT_BYTES]; N]),
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slot_bytes: MAX_SLOT_BYTES,
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word_bytes,
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write_slot: UnsafeCell::new(0),
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write_off: UnsafeCell::new(0),
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produced: AtomicUsize::new(0),
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consumed: AtomicUsize::new(0),
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safety_gap: 1,
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produced_bytes: AtomicUsize::new(0),
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consumed_bytes: AtomicUsize::new(0),
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})
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}
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/// Optional: adjust safety gap (defaults to 1 empty slot).
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pub fn set_safety_gap(&mut self, gap_slots: usize) {
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self.safety_gap = gap_slots.min(N);
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}
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pub fn slot_size(&self) -> usize {
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self.slot_bytes
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}
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pub fn set_slot_size(&mut self, slot_bytes: usize) -> Result<(), ConfigError> {
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if slot_bytes == 0 {
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return Err(ConfigError::SlotTooSmall);
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}
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if slot_bytes > MAX_SLOT_BYTES {
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return Err(ConfigError::SlotTooLarge);
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}
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if slot_bytes % self.word_bytes != 0 {
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return Err(ConfigError::SlotNotAligned);
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}
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self.slot_bytes = slot_bytes;
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self.reset_producer();
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Ok(())
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}
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/// Producer: copy into ring; commits whole slots; reports overflow by returning dropped bytes.
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pub fn push(&self, mut data: &[u8]) -> PushResult {
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let mut written = 0usize;
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let write_slot = unsafe { &mut *self.write_slot.get() };
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let write_off = unsafe { &mut *self.write_off.get() };
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let slots = unsafe { &mut *self.slots.get() };
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defmt::debug!(
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"produced={} consumed={} fill={}",
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self.produced(),
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self.consumed(),
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self.fill_slots()
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);
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while !data.is_empty() {
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if self.is_full_for_producer() {
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break;
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}
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let cap = self.slot_bytes - *write_off;
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let n = core::cmp::min(cap, data.len());
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unsafe {
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let dst = slots[*write_slot].as_mut_ptr().add(*write_off);
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copy_nonoverlapping(data.as_ptr(), dst, n);
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}
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*write_off += n;
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written += n;
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data = &data[n..];
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if *write_off == self.slot_bytes {
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// publish completed slot
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compiler_fence(Ordering::Release);
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self.produced.fetch_add(1, Ordering::Release);
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*write_slot = (*write_slot + 1) % N;
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*write_off = 0;
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}
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}
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self.produced_bytes.fetch_add(written, Ordering::Release);
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PushResult {
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written,
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dropped: data.len(),
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}
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}
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/// Call from DMA IRQ bookkeeping when a slot has been consumed.
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pub fn advance_consumed(&self, slots: usize) -> Result<(), DmaError> {
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let produced = self.produced.load(Ordering::Acquire);
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let consumed = self.consumed.load(Ordering::Relaxed);
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if consumed < produced {
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self.consumed.fetch_add(slots, Ordering::Release);
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self.consumed_bytes
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.fetch_add(slots * self.slot_bytes, Ordering::Relaxed);
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Ok(())
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} else {
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defmt::error!("DMA underrun!");
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Err(DmaError::Underrun)
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}
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}
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pub fn produced(&self) -> usize {
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self.produced.load(Ordering::Acquire)
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}
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pub fn consumed(&self) -> usize {
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self.consumed.load(Ordering::Acquire)
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}
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pub fn consumed_bytes(&self) -> usize {
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self.consumed.load(Ordering::Acquire) * self.slot_bytes
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+ (self.dma.channel19.xfercfg.read().bits() as usize >> 16 & 0x3ff)
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}
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pub fn fill_slots(&self) -> usize {
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self.produced().wrapping_sub(self.consumed())
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}
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pub fn init(&self) {
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self.init_descriptors();
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// Descriptor table base
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let desc = unsafe { &*self.desc.get() };
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let base = self.channel_desc.get() as u32;
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self.dma.srambase.write(|w| unsafe { w.bits(base) });
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self.dma
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.channel19
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.cfg
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.write(|w| w.periphreqen().enabled().hwtrigen().disabled());
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self.dma
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.channel19
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.xfercfg
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.write(|w| unsafe { w.bits(desc.d[0].xfercfg) });
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self.dma.enableclr0.write(|w| unsafe { w.bits(1 << 19) });
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self.dma.ctrl.write(|w| w.enable().enabled());
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self.dma.setvalid0.write(|w| unsafe { w.bits(1 << 19) });
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self.dma.intenset0.write(|w| unsafe { w.bits(1 << 19) });
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self.dma.settrig0.write(|w| unsafe { w.bits(1 << 19) });
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}
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pub fn run(&self) {
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self.dma.enableset0.write(|w| unsafe { w.bits(1 << 19) });
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}
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pub fn stop(&self) {
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self.dma.enableclr0.write(|w| unsafe { w.bits(1 << 19) });
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nb::block!(if (self.dma.busy0.read().bits() & 1 << 19) == 0 {
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Ok(())
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} else {
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Err(nb::Error::<Infallible>::WouldBlock)
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});
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self.dma.abort0.write(|w| unsafe { w.bits(1 << 19) });
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self.reset_producer();
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}
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fn reset_producer(&self) {
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unsafe {
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*(&mut *self.write_slot.get()) = 0;
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*(&mut *self.write_off.get()) = 0;
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}
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self.produced.store(0, Ordering::Relaxed);
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self.produced_bytes.store(0, Ordering::Relaxed);
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self.consumed.store(0, Ordering::Relaxed);
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self.consumed_bytes.store(0, Ordering::Relaxed);
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}
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fn is_full_for_producer(&self) -> bool {
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let fill = self.fill_slots();
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fill >= N.wrapping_sub(self.safety_gap)
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}
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fn reset_producer_init_only(&self) {
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unsafe {
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*self.write_slot.get() = 0;
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}
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unsafe {
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*self.write_off.get() = 0;
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}
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self.produced.store(0, Ordering::Relaxed);
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self.consumed.store(0, Ordering::Relaxed);
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self.produced_bytes.store(0, Ordering::Relaxed);
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self.consumed_bytes.store(0, Ordering::Relaxed);
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}
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fn init_descriptors(&self) {
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let slots = unsafe { &mut *self.slots.get() };
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let desc = unsafe { &mut *self.desc.get() };
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let chan_desc = unsafe { &mut *self.channel_desc.get() };
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defmt::info!("slots base: &{:x}", self.slots.get());
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// Pre-fill with silence so underrun replays silence.
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for i in 0..N {
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slots[i][..self.slot_bytes].fill(0);
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}
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let transfers = (self.slot_bytes / self.word_bytes) as u32;
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for i in 0..N {
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let src_start = slots[i].as_ptr() as usize;
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let src_end = (src_start + self.slot_bytes - self.word_bytes) as *const u8;
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let next = &desc.d[(i + 1) % N] as *const DmaDescriptor;
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desc.d[i] = DmaDescriptor {
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xfercfg: encode_xfercfg(
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true, // valid
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true, // reload
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false, // swtrig (we use XFERCFG SWTRIG kick)
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false, // clrtrig
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true, // intA
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false, // intB
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self.word_bytes as u32,
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1, // src_inc
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0, // dst_inc
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transfers,
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),
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src_end,
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dst_end: self.dst_reg,
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next,
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};
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}
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chan_desc.d[19] = desc.d[0];
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chan_desc.d[19].xfercfg = 0;
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// reset producer indices + counters (init-only action)
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self.reset_producer_init_only();
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}
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}
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unsafe impl<const N: usize, const MAX_SLOT_BYTES: usize> Sync for DmaRing<N, MAX_SLOT_BYTES> {}
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/// XFERCFG encoding follows the common LPC DMA layout:
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/// - SETINTA at bit4, SETINTB at bit5
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/// - WIDTH at bits 9:8
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/// - SRCINC at bits 13:12
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/// - DSTINC at bits 15:14
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/// - XFERCOUNT at bits 25:16
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/// This layout is shown in LPC DMA examples. [5](https://www.kernel.org/doc/html/latest/core-api/dma-api-howto.html)
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fn encode_xfercfg(
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cfgvalid: bool,
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reload: bool,
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swtrig: bool,
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clrtrig: bool,
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inta: bool,
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intb: bool,
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width_bytes: u32,
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src_inc: u32,
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dst_inc: u32,
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transfers: u32,
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) -> u32 {
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let width_code = match width_bytes {
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1 => 0,
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2 => 1,
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4 => 2,
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_ => 0,
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};
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let count_field = transfers.saturating_sub(1) & 0x3FF;
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((cfgvalid as u32) << 0)
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| ((reload as u32) << 1)
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| ((swtrig as u32) << 2)
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| ((clrtrig as u32) << 3)
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| ((inta as u32) << 4)
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| ((intb as u32) << 5)
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| ((width_code & 0x3) << 8)
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| ((src_inc & 0x3) << 12)
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| ((dst_inc & 0x3) << 14)
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| (count_field << 16)
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}
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@@ -0,0 +1,367 @@
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//! Contains hardware setup unrelated to Usb Audio Class implementation
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use crate::hal;
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use core::cell::{OnceCell, UnsafeCell};
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use core::mem::MaybeUninit;
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use core::ptr::null_mut;
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use crate::Syscon;
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use crate::{MCLK_FREQ, SAMPLE_RATE, pac};
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use defmt::debug;
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use hal::{
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Iocon, Pin,
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drivers::pins,
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prelude::*,
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traits::wg::digital::v2::{OutputPin, ToggleableOutputPin},
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typestates::pin::{gpio::direction::Output, state::Gpio},
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};
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use lpc55_hal::Enabled;
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use static_cell::StaticCell;
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pub(crate) struct PllConstants {
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pub m: u16, // 1-65535
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pub n: u8, // 1-255
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pub p: u8, // 1-31
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pub selp: u8, // 5 bits
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pub seli: u8, // 6 bits
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}
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impl PllConstants {
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pub(crate) const fn new(n: u8, m: u16, p: u8) -> Self {
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assert!(n != 0, "1 <= N <= 255");
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assert!(m != 0, "1 <= M <= 65535");
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assert!(p != 0 && p <= 31, "1 <= P <= 31");
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// Following ripped from lpc55-hal and made const
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// UM 4.6.6.3.2
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let selp = {
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let v = (m >> 2) + 1;
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if v < 31 { v } else { 31 }
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} as u8;
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let seli = {
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let v = match m {
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m if m >= 8000 => 1,
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m if m >= 122 => 8000 / m,
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_ => 2 * (m >> 2) + 3,
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};
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if v < 63 { v } else { 63 }
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} as u8;
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// let seli = min(2*(m >> 2) + 3, 63);
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Self {
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n,
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m,
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p,
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selp,
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seli,
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}
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}
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}
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impl defmt::Format for PllConstants {
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fn format(&self, fmt: defmt::Formatter) {
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let factor = f32::from(self.m) / (f32::from(self.n) * 2.0 * f32::from(self.p));
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defmt::write!(
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fmt,
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"m: {} n: {} p: {} selp: {} seli: {} fout: fin * {}",
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self.m,
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self.n,
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self.p,
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self.selp,
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self.seli,
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factor
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);
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}
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}
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||||
// Fo = M/(N*2*P) * Fin
|
||||
// Fo = 3072/(125*2*8) * 16MHz = 24.576MHz
|
||||
const AUDIO_PLL: PllConstants = PllConstants::new(125, 3072, 8);
|
||||
|
||||
// Set PLL0 to 24.576MHz, start, and wait for lock
|
||||
// This is not exposed by lpc55-hal, unfortunately. Copy their implementation here.
|
||||
pub(crate) fn init_audio_pll() {
|
||||
let syscon = unsafe { &*pac::SYSCON::ptr() };
|
||||
let pmc = unsafe { &*pac::PMC::ptr() };
|
||||
let anactrl = unsafe { &*pac::ANACTRL::ptr() };
|
||||
|
||||
debug!("start clk_in");
|
||||
pmc.pdruncfg0
|
||||
.modify(|_, w| w.pden_xtal32m().poweredon().pden_ldoxo32m().poweredon());
|
||||
syscon.clock_ctrl.modify(|_, w| w.clkin_ena().enable());
|
||||
anactrl
|
||||
.xo32m_ctrl
|
||||
.modify(|_, w| w.enable_system_clk_out().enable());
|
||||
|
||||
debug!("init pll0: {}", AUDIO_PLL);
|
||||
pmc.pdruncfg0
|
||||
.modify(|_, w| w.pden_pll0().poweredoff().pden_pll0_sscg().poweredoff());
|
||||
syscon.pll0clksel.write(|w| w.sel().enum_0x1()); // clk_in
|
||||
syscon.pll0ctrl.write(|w| unsafe {
|
||||
w.clken()
|
||||
.enable()
|
||||
.seli()
|
||||
.bits(AUDIO_PLL.seli)
|
||||
.selp()
|
||||
.bits(AUDIO_PLL.selp)
|
||||
});
|
||||
|
||||
syscon
|
||||
.pll0ndec
|
||||
.write(|w| unsafe { w.ndiv().bits(AUDIO_PLL.n) });
|
||||
syscon.pll0ndec.write(|w| unsafe {
|
||||
w.ndiv().bits(AUDIO_PLL.n).nreq().set_bit() // latch
|
||||
});
|
||||
|
||||
syscon
|
||||
.pll0pdec
|
||||
.write(|w| unsafe { w.pdiv().bits(AUDIO_PLL.p) });
|
||||
syscon.pll0pdec.write(|w| unsafe {
|
||||
w.pdiv().bits(AUDIO_PLL.p).preq().set_bit() // latch
|
||||
});
|
||||
|
||||
syscon.pll0sscg0.write(|w| unsafe { w.md_lbs().bits(0) });
|
||||
|
||||
syscon
|
||||
.pll0sscg1
|
||||
.write(|w| unsafe { w.mdiv_ext().bits(AUDIO_PLL.m).sel_ext().set_bit() });
|
||||
syscon.pll0sscg1.write(|w| unsafe {
|
||||
w.mdiv_ext()
|
||||
.bits(AUDIO_PLL.m)
|
||||
.sel_ext()
|
||||
.set_bit()
|
||||
.mreq()
|
||||
.set_bit() // latch
|
||||
.md_req()
|
||||
.set_bit() // latch
|
||||
});
|
||||
|
||||
pmc.pdruncfg0
|
||||
.modify(|_, w| w.pden_pll0().poweredon().pden_pll0_sscg().poweredon());
|
||||
debug!("pll0 wait for lock");
|
||||
let mut i = 0usize;
|
||||
while syscon.pll0stat.read().lock().bit_is_clear() {
|
||||
i += 1;
|
||||
}
|
||||
debug!("pll0 locked after {} tries", i);
|
||||
}
|
||||
|
||||
const SYS_PLL: PllConstants = PllConstants::new(4, 75, 1); // 150MHz
|
||||
|
||||
pub(crate) fn init_sys_pll1() {
|
||||
let syscon = unsafe { &*pac::SYSCON::ptr() };
|
||||
let pmc = unsafe { &*pac::PMC::ptr() };
|
||||
let anactrl = unsafe { &*pac::ANACTRL::ptr() };
|
||||
|
||||
debug!("start clk_in");
|
||||
pmc.pdruncfg0
|
||||
.modify(|_, w| w.pden_xtal32m().poweredon().pden_ldoxo32m().poweredon());
|
||||
syscon.clock_ctrl.modify(|_, w| w.clkin_ena().enable());
|
||||
anactrl
|
||||
.xo32m_ctrl
|
||||
.modify(|_, w| w.enable_system_clk_out().enable());
|
||||
|
||||
debug!("init pll1: {}", SYS_PLL);
|
||||
pmc.pdruncfg0.modify(|_, w| w.pden_pll1().poweredoff());
|
||||
syscon.pll1clksel.write(|w| w.sel().enum_0x1()); // clk_in
|
||||
syscon.pll1ctrl.write(|w| unsafe {
|
||||
w.clken()
|
||||
.enable()
|
||||
.seli()
|
||||
.bits(SYS_PLL.seli)
|
||||
.selp()
|
||||
.bits(SYS_PLL.selp)
|
||||
});
|
||||
|
||||
syscon
|
||||
.pll1ndec
|
||||
.write(|w| unsafe { w.ndiv().bits(SYS_PLL.n) });
|
||||
syscon.pll1ndec.write(|w| unsafe {
|
||||
w.ndiv().bits(SYS_PLL.n).nreq().set_bit() // latch
|
||||
});
|
||||
syscon
|
||||
.pll1mdec
|
||||
.write(|w| unsafe { w.mdiv().bits(SYS_PLL.m) });
|
||||
syscon
|
||||
.pll1pdec
|
||||
.write(|w| unsafe { w.pdiv().bits(SYS_PLL.p) });
|
||||
syscon.pll1pdec.write(|w| unsafe {
|
||||
w.pdiv().bits(SYS_PLL.p).preq().set_bit() // latch
|
||||
});
|
||||
|
||||
pmc.pdruncfg0.modify(|_, w| w.pden_pll1().poweredon());
|
||||
debug!("pll1 wait for lock");
|
||||
let mut i = 0usize;
|
||||
while syscon.pll1stat.read().lock().bit_is_clear() {
|
||||
i += 1;
|
||||
}
|
||||
debug!("pll1 locked after {} tries", i);
|
||||
// switch system clock to pll1
|
||||
syscon.fmccr.modify(|_, w| w.flashtim().flashtim11());
|
||||
syscon.mainclkselb.modify(|_, w| w.sel().enum_0x2()); // pll1
|
||||
}
|
||||
|
||||
pub struct I2sTx {
|
||||
pub i2s: pac::I2S7,
|
||||
}
|
||||
|
||||
pub fn init_i2s(mut fc7: pac::FLEXCOMM7, i2s7: pac::I2S7, syscon: &mut Syscon) -> I2sTx {
|
||||
defmt::debug!("init i2s");
|
||||
// Enable BOTH
|
||||
syscon.reset(&mut fc7);
|
||||
syscon.enable_clock(&mut fc7);
|
||||
|
||||
unsafe {
|
||||
pac::IOCON::ptr().as_ref().unwrap().pio1_31.modify(|_, w| {
|
||||
w.func()
|
||||
.alt1()
|
||||
.mode()
|
||||
.inactive()
|
||||
.slew()
|
||||
.fast()
|
||||
.invert()
|
||||
.disabled()
|
||||
.digimode()
|
||||
.digital()
|
||||
.od()
|
||||
.normal()
|
||||
});
|
||||
pac::SYSCON::ptr()
|
||||
.as_ref()
|
||||
.unwrap()
|
||||
.fcclksel7()
|
||||
.modify(|_, w| w.sel().enum_0x5()); // MCLK
|
||||
pac::SYSCON::ptr()
|
||||
.as_ref()
|
||||
.unwrap()
|
||||
.mclkclksel
|
||||
.modify(|_, w| w.sel().enum_0x1()); // PLL0
|
||||
pac::SYSCON::ptr()
|
||||
.as_ref()
|
||||
.unwrap()
|
||||
.mclkdiv
|
||||
.modify(|_, w| w.div().bits(1).halt().run().reset().released()); // div by 2 = PLL0 fout / 2 = 12.288MHz, max for WM8904 @ 96k
|
||||
pac::SYSCON::ptr()
|
||||
.as_ref()
|
||||
.unwrap()
|
||||
.mclkio
|
||||
.modify(|_, w| w.mclkio().output());
|
||||
};
|
||||
|
||||
// Select I2S TX function
|
||||
fc7.pselid.write(|w| w.persel().i2s_transmit());
|
||||
|
||||
let regs = i2s7;
|
||||
|
||||
// Enable TX FIFO only
|
||||
regs.fifocfg.modify(|_, w| {
|
||||
w.enabletx()
|
||||
.enabled()
|
||||
.enablerx()
|
||||
.disabled()
|
||||
.dmatx()
|
||||
.disabled()
|
||||
.txi2se0()
|
||||
.zero()
|
||||
});
|
||||
regs.fifotrig.modify(|_, w| unsafe { w.txlvl().bits(6) });
|
||||
|
||||
// Flush
|
||||
regs.fifocfg.modify(|_, w| w.emptytx().set_bit());
|
||||
|
||||
regs.cfg2
|
||||
.modify(|_, w| unsafe { w.position().bits(0).framelen().bits(63) }); // framelen = 64
|
||||
|
||||
let bclk_div = (MCLK_FREQ / SAMPLE_RATE / 64) as u16;
|
||||
regs.div
|
||||
.modify(|_, w| unsafe { w.div().bits(bclk_div - 1) }); // Clock source is MCLK (12.288MHz) / 4 = 3MHz
|
||||
|
||||
// Config
|
||||
regs.cfg1.modify(|_, w| unsafe {
|
||||
w.mstslvcfg()
|
||||
.normal_master()
|
||||
.onechannel()
|
||||
.dual_channel()
|
||||
.datalen()
|
||||
.bits(31)
|
||||
.mainenable()
|
||||
.enabled()
|
||||
.mode()
|
||||
.classic_mode()
|
||||
.datapause()
|
||||
.normal()
|
||||
});
|
||||
|
||||
I2sTx { i2s: regs }
|
||||
}
|
||||
|
||||
pub struct SharedLed<T: OutputPin> {
|
||||
inner: UnsafeCell<T>,
|
||||
}
|
||||
unsafe impl<T: OutputPin> Sync for SharedLed<T> {}
|
||||
impl<T: OutputPin> SharedLed<T> {
|
||||
pub fn new(inner: T) -> Self {
|
||||
Self {
|
||||
inner: UnsafeCell::new(inner),
|
||||
}
|
||||
}
|
||||
pub fn on(&self) {
|
||||
unsafe {
|
||||
(*self.inner.get()).set_low().ok();
|
||||
}
|
||||
}
|
||||
pub fn off(&self) {
|
||||
unsafe {
|
||||
(*self.inner.get()).set_high().ok();
|
||||
}
|
||||
}
|
||||
}
|
||||
impl<T: OutputPin + ToggleableOutputPin> SharedLed<T> {
|
||||
pub fn toggle(&self) {
|
||||
unsafe {
|
||||
(*self.inner.get()).toggle().ok();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
type RedLed = Pin<pins::Pio1_6, Gpio<Output>>;
|
||||
type GreenLed = Pin<pins::Pio1_7, Gpio<Output>>;
|
||||
type BlueLed = Pin<pins::Pio1_4, Gpio<Output>>;
|
||||
pub static RED_LED: MaybeUninit<SharedLed<RedLed>> = MaybeUninit::uninit();
|
||||
pub static GREEN_LED: MaybeUninit<SharedLed<GreenLed>> = MaybeUninit::uninit();
|
||||
pub static BLUE_LED: MaybeUninit<SharedLed<BlueLed>> = MaybeUninit::uninit();
|
||||
|
||||
pub fn init_leds(iocon: &mut Iocon<Enabled>, gpio: &mut hal::Gpio<Enabled>) {
|
||||
let red_led = SharedLed::new(
|
||||
pins::Pio1_6::take()
|
||||
.unwrap()
|
||||
.into_gpio_pin(iocon, gpio)
|
||||
.into_output_low(),
|
||||
);
|
||||
let green_led = SharedLed::new(
|
||||
pins::Pio1_7::take()
|
||||
.unwrap()
|
||||
.into_gpio_pin(iocon, gpio)
|
||||
.into_output_low(),
|
||||
);
|
||||
let blue_led = SharedLed::new(
|
||||
pins::Pio1_4::take()
|
||||
.unwrap()
|
||||
.into_gpio_pin(iocon, gpio)
|
||||
.into_output_low(),
|
||||
);
|
||||
unsafe {
|
||||
core::ptr::write(RED_LED.as_ptr() as *mut SharedLed<RedLed>, red_led);
|
||||
core::ptr::write(GREEN_LED.as_ptr() as *mut SharedLed<GreenLed>, green_led);
|
||||
core::ptr::write(BLUE_LED.as_ptr() as *mut SharedLed<BlueLed>, blue_led);
|
||||
}
|
||||
}
|
||||
pub fn red_led() -> &'static SharedLed<RedLed> {
|
||||
unsafe { &*RED_LED.as_ptr() }
|
||||
}
|
||||
pub fn green_led() -> &'static SharedLed<GreenLed> {
|
||||
unsafe { &*GREEN_LED.as_ptr() }
|
||||
}
|
||||
pub fn blue_led() -> &'static SharedLed<BlueLed> {
|
||||
unsafe { &*BLUE_LED.as_ptr() }
|
||||
}
|
||||
@@ -0,0 +1,400 @@
|
||||
//! Interrupt driven example for the LPCXpresso55S28 demo board
|
||||
//!
|
||||
//! Uses the onboard WM8904 DAC at 48KHz. Clock is generated by PLL0. Simple PI feedback
|
||||
//! is implemented.
|
||||
//!
|
||||
//! Packets from USB are placed a `heapless::spsc::Queue`. They are consumed
|
||||
//! by the I2S FIFO in the FLEXCOMM7 interrupt.
|
||||
#![no_main]
|
||||
#![no_std]
|
||||
|
||||
#[cfg(all(feature = "usbfs", feature = "usbhs"))]
|
||||
compile_error!("Choose one USB peripheral, usbfs and usbhs cannot be used together");
|
||||
|
||||
extern crate panic_probe;
|
||||
#[defmt::panic_handler]
|
||||
fn panic() -> ! {
|
||||
panic_probe::hard_fault()
|
||||
}
|
||||
|
||||
use core::sync::atomic::{AtomicBool, Ordering};
|
||||
use cortex_m_rt::entry;
|
||||
use defmt::debug;
|
||||
use defmt_rtt as _;
|
||||
use hal::raw as pac;
|
||||
use hal::{
|
||||
Syscon,
|
||||
drivers::{Timer, UsbBus, pins},
|
||||
prelude::*,
|
||||
time::Hertz,
|
||||
};
|
||||
use lpc55_hal as hal;
|
||||
use pac::interrupt;
|
||||
use static_cell::StaticCell;
|
||||
use usb_device::{
|
||||
bus::{self},
|
||||
device::{StringDescriptors, UsbDeviceBuilder, UsbVidPid},
|
||||
endpoint::IsochronousSynchronizationType,
|
||||
};
|
||||
use usbd_uac2::UsbIsochronousFeedback;
|
||||
use usbd_uac2::{
|
||||
self, AudioClassConfig, RangeEntry, TerminalConfig, UsbAudioClass, UsbAudioClockImpl, UsbSpeed,
|
||||
constants::{FunctionCode, TerminalType},
|
||||
descriptors::{ChannelConfig, ClockType, FormatType1, LockDelay},
|
||||
};
|
||||
|
||||
use crate::dma::DmaRing;
|
||||
use crate::hw::{I2sTx, blue_led, green_led, red_led};
|
||||
|
||||
mod dma;
|
||||
mod hw;
|
||||
mod wm8904;
|
||||
|
||||
const CODEC_I2C_ADDR: u8 = 0b0011010;
|
||||
const MCLK_FREQ: u32 = 12288000;
|
||||
const SAMPLE_RATE: u32 = 96000;
|
||||
//latency ≈ (current_fill × FRAMES_PER_SLOT)
|
||||
// + FRAMES_PER_SLOT/2 - average DMA transfer position
|
||||
// + 8 - FIFO depth @ 32-bit samples
|
||||
const BYTES_PER_SAMPLE: usize = 4; // 32 bit samples
|
||||
const BYTES_PER_FRAME: usize = BYTES_PER_SAMPLE * 2; // 2 channels
|
||||
const FRAMES_PER_SLOT: usize = SAMPLE_RATE as usize / 2000; // run the DMA at 2khz
|
||||
const SLOT_SIZE_BYTES: usize = FRAMES_PER_SLOT * BYTES_PER_FRAME; // run the DMA at 2khz
|
||||
const N_SLOTS: usize = 32;
|
||||
const FILL_TARGET: i32 = (FRAMES_PER_SLOT * N_SLOTS) as i32 / 2;
|
||||
|
||||
struct Clock {}
|
||||
impl Clock {
|
||||
const RATES: [RangeEntry<u32>; 1] = [RangeEntry::new_fixed(SAMPLE_RATE)];
|
||||
}
|
||||
impl UsbAudioClockImpl for Clock {
|
||||
const CLOCK_TYPE: usbd_uac2::descriptors::ClockType = ClockType::InternalFixed;
|
||||
const SOF_SYNC: bool = false;
|
||||
fn get_sample_rate(&self) -> u32 {
|
||||
Clock::RATES[0].min
|
||||
}
|
||||
fn get_rates(
|
||||
&self,
|
||||
) -> core::result::Result<&[usbd_uac2::RangeEntry<u32>], usbd_uac2::UsbAudioClassError> {
|
||||
Ok(&Clock::RATES)
|
||||
}
|
||||
fn get_clock_validity(&self) -> core::result::Result<bool, usbd_uac2::UsbAudioClassError> {
|
||||
Ok(true)
|
||||
}
|
||||
}
|
||||
|
||||
static DMA_RING: StaticCell<DmaRing<N_SLOTS, SLOT_SIZE_BYTES>> = StaticCell::new();
|
||||
static mut DMA_RING_REF: Option<&'static DmaRing<N_SLOTS, SLOT_SIZE_BYTES>> = None;
|
||||
#[inline]
|
||||
fn dma_ring() -> &'static DmaRing<N_SLOTS, SLOT_SIZE_BYTES> {
|
||||
unsafe { DMA_RING_REF.unwrap() }
|
||||
}
|
||||
|
||||
#[interrupt]
|
||||
fn DMA0() {
|
||||
let dma = unsafe { &*pac::DMA0::ptr() };
|
||||
|
||||
let inta = dma.inta0.read().bits();
|
||||
let err = dma.errint0.read().bits();
|
||||
|
||||
if (err & (1 << 19)) != 0 {
|
||||
let live = dma.channel19.xfercfg.read().bits();
|
||||
|
||||
let desc = unsafe { &*dma_ring().channel_desc.get() };
|
||||
let mem = desc.d[19];
|
||||
defmt::error!(
|
||||
"DMA error ch19: live={=u32:08x} INTA={=u32:x} ERR={=u32:x}\n desc: {}",
|
||||
live,
|
||||
inta,
|
||||
err,
|
||||
mem
|
||||
);
|
||||
red_led().on();
|
||||
dma.errint0.write(|w| unsafe { w.bits(1 << 19) });
|
||||
}
|
||||
|
||||
if (inta & (1 << 19)) != 0 {
|
||||
dma.inta0.write(|w| unsafe { w.bits(1 << 19) });
|
||||
if dma_ring().advance_consumed(1).is_err() {
|
||||
red_led().on();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
struct Audio<'a, const N: usize, const MAX_SLOT_BYTES: usize> {
|
||||
running: AtomicBool,
|
||||
i2s: I2sTx,
|
||||
dma: &'a DmaRing<N, MAX_SLOT_BYTES>,
|
||||
}
|
||||
impl<const N: usize, const MAX_SLOT_BYTES: usize> Audio<'_, N, MAX_SLOT_BYTES> {
|
||||
fn start(&self) {
|
||||
red_led().off(); // clear any dma error
|
||||
self.running.store(false, Ordering::Relaxed);
|
||||
|
||||
defmt::info!("playback starting (DMA)");
|
||||
|
||||
let i2s = &self.i2s.i2s;
|
||||
i2s.fifotrig
|
||||
.modify(|_, w| unsafe { w.txlvl().bits(6).txlvlena().enabled() });
|
||||
|
||||
// Enable TX FIFO
|
||||
i2s.fifocfg
|
||||
.modify(|_, w| w.enabletx().enabled().dmatx().enabled());
|
||||
dma_ring().init();
|
||||
// Enable DMA interrupt (channel 19)
|
||||
unsafe { pac::NVIC::unmask(pac::Interrupt::DMA0) };
|
||||
|
||||
green_led().on();
|
||||
}
|
||||
fn stop(&self) {
|
||||
// If we don't disable interrupts while stopped, we will underflow constantly and continuously refill the fifo with 0s
|
||||
// We could actually stop the I2S here, but sometimes that makes the DAC misbehave. The peripheral is configured to send
|
||||
// 0s when the FIFO is empty, so this is fine.
|
||||
self.running.store(false, Ordering::Relaxed);
|
||||
dma_ring().stop();
|
||||
defmt::info!("playback stopped");
|
||||
pac::NVIC::mask(pac::Interrupt::DMA0);
|
||||
green_led().off();
|
||||
blue_led().off();
|
||||
}
|
||||
}
|
||||
impl<const N: usize, const MAX_SLOT_BYTES: usize, B: bus::UsbBus> UsbAudioClass<'_, B>
|
||||
for Audio<'_, N, MAX_SLOT_BYTES>
|
||||
{
|
||||
fn alternate_setting_changed(&mut self, _terminal: usb_device::UsbDirection, alt_setting: u8) {
|
||||
// alt setting 0 means stopped
|
||||
match alt_setting {
|
||||
0 => self.stop(),
|
||||
1 => self.start(),
|
||||
_ => defmt::error!("unexpected alt setting {}", alt_setting),
|
||||
}
|
||||
}
|
||||
fn audio_data_rx(
|
||||
&mut self,
|
||||
ep: &usb_device::endpoint::Endpoint<'_, B, usb_device::endpoint::Out>,
|
||||
) {
|
||||
// Buffer must fit 125us of audio data (based on how `usbd_uac2` sets up the descriptors).
|
||||
let mut buf = [0; SAMPLE_RATE.div_ceil(8000) as usize * BYTES_PER_FRAME];
|
||||
|
||||
let len = match ep.read(&mut buf) {
|
||||
Ok(len) => len,
|
||||
Err(_) => {
|
||||
defmt::error!("usb error in rx callback");
|
||||
return;
|
||||
}
|
||||
};
|
||||
|
||||
let buf = &buf[..len];
|
||||
let res = self.dma.push(buf);
|
||||
|
||||
if res.dropped != 0 {
|
||||
// Overflow: some or all bytes couldn't be queued.
|
||||
blue_led().toggle();
|
||||
defmt::error!(
|
||||
"overflowed dma ring, asked {}, wrote {}, dropped {}",
|
||||
buf.len(),
|
||||
res.written,
|
||||
res.dropped
|
||||
);
|
||||
}
|
||||
// If we're not running yet, wait until we reach 50% full then enable DMA requests
|
||||
if !self.running.load(Ordering::Relaxed) && self.dma.fill_slots() >= (N_SLOTS / 2) {
|
||||
defmt::debug!(
|
||||
"buffer has {} slots, start dma transfers",
|
||||
self.dma.fill_slots()
|
||||
);
|
||||
self.dma.run();
|
||||
self.running.store(true, Ordering::Relaxed)
|
||||
}
|
||||
}
|
||||
|
||||
/// Provide rate feedback to the host, so that it doesn't over- or underflow
|
||||
/// the buffer. Proportional-only control is stable with normal hosts,
|
||||
/// adding an I term with proper tuning (quite weak) would stabilize the
|
||||
/// rate reported to the host but is not necessary for basic playback.
|
||||
fn feedback(&mut self, nominal_rate: UsbIsochronousFeedback) -> Option<UsbIsochronousFeedback> {
|
||||
const MAX_CORRECTION: i32 = 1 << 10; // ~1.6%
|
||||
|
||||
let produced_bytes = self.dma.produced_bytes.load(Ordering::Acquire);
|
||||
let consumed_bytes = self.dma.consumed_bytes();
|
||||
|
||||
let valid = produced_bytes >= consumed_bytes; // else we are in underrun condition
|
||||
|
||||
let fill_frames = if valid {
|
||||
(produced_bytes - consumed_bytes) as i32 / BYTES_PER_FRAME as i32
|
||||
} else {
|
||||
// we will emit a canonical error in the DMA ISR
|
||||
defmt::debug!("[fb] dma underrun detected");
|
||||
0
|
||||
};
|
||||
|
||||
let mut error = fill_frames - FILL_TARGET;
|
||||
error = error.clamp(-32, 32); // avoid huge spikes
|
||||
|
||||
let p = error * 256;
|
||||
let i = 0; // placeholder
|
||||
|
||||
let correction = -(p + i);
|
||||
|
||||
let nominal_v = nominal_rate.to_u32_12_13() as i32;
|
||||
|
||||
let mut v = nominal_v + correction;
|
||||
|
||||
v = v.clamp(nominal_v - MAX_CORRECTION, nominal_v + MAX_CORRECTION);
|
||||
|
||||
defmt::debug!(
|
||||
"valid:{} fill:{} err:{} fb:{=u32:x}",
|
||||
valid,
|
||||
fill_frames,
|
||||
error,
|
||||
v as u32
|
||||
);
|
||||
|
||||
Some(UsbIsochronousFeedback::new(v as u32))
|
||||
}
|
||||
}
|
||||
|
||||
#[entry]
|
||||
fn main() -> ! {
|
||||
let hal = hal::new();
|
||||
|
||||
let mut anactrl = hal.anactrl;
|
||||
let mut pmc = hal.pmc;
|
||||
let mut syscon = hal.syscon;
|
||||
|
||||
let mut gpio = hal.gpio.enabled(&mut syscon);
|
||||
let mut iocon = hal.iocon.enabled(&mut syscon);
|
||||
|
||||
debug!("start");
|
||||
|
||||
hw::init_leds(&mut iocon, &mut gpio);
|
||||
|
||||
debug!("iocon");
|
||||
let usb0_vbus_pin = pins::Pio0_22::take()
|
||||
.unwrap()
|
||||
.into_usb0_vbus_pin(&mut iocon);
|
||||
let codec_i2c_pins = (
|
||||
pins::Pio1_20::take().unwrap().into_i2c4_scl_pin(&mut iocon),
|
||||
pins::Pio1_21::take().unwrap().into_i2c4_sda_pin(&mut iocon),
|
||||
);
|
||||
// We can initialize and iocon these, but there is no peripheral, so they do not get used
|
||||
let _codec_i2s_pins = (
|
||||
pins::Pio0_21::take().unwrap().into_spi7_sck_pin(&mut iocon),
|
||||
pins::Pio0_20::take().unwrap().into_i2s7_sda_pin(&mut iocon),
|
||||
pins::Pio0_19::take().unwrap().into_i2s7_ws_pin(&mut iocon),
|
||||
pins::Pio1_31::take().unwrap(), // MCLK
|
||||
);
|
||||
|
||||
debug!("clocks");
|
||||
// Run the system clock at 96MHz. The lpc55-hal will run it from the FRO. But we won't actually use these clocks, we just need the guards...
|
||||
let clocks = hal::ClockRequirements::default()
|
||||
.system_frequency(96.MHz())
|
||||
.configure(&mut anactrl, &mut pmc, &mut syscon)
|
||||
.unwrap();
|
||||
let mut _delay_timer = Timer::new(
|
||||
hal.ctimer
|
||||
.0
|
||||
.enabled(&mut syscon, clocks.support_1mhz_fro_token().unwrap()),
|
||||
);
|
||||
// Start PLL1 at 150MHz as main system clock
|
||||
hw::init_sys_pll1();
|
||||
// Start PLL0 at 24.576MHz as the audio clock. The FRO cannot evenly divide
|
||||
// any common audio frequencies and is not particularly stable anyway.
|
||||
hw::init_audio_pll();
|
||||
|
||||
debug!("peripherals");
|
||||
|
||||
let i2c_peripheral = hal
|
||||
.flexcomm
|
||||
.4
|
||||
.enabled_as_i2c(&mut syscon, &clocks.support_flexcomm_token().unwrap());
|
||||
let mut i2c_bus = I2cMaster::new(
|
||||
i2c_peripheral,
|
||||
codec_i2c_pins,
|
||||
Hertz::try_from(400.kHz()).unwrap(),
|
||||
);
|
||||
|
||||
let i2s_peripheral = {
|
||||
let fc7 = hal.flexcomm.7.release();
|
||||
hw::init_i2s(fc7.0, fc7.2, &mut syscon)
|
||||
};
|
||||
|
||||
#[cfg(feature = "usbhs")]
|
||||
let (usb_speed, usb_peripheral) = (
|
||||
UsbSpeed::High,
|
||||
hal.usbhs.enabled_as_device(
|
||||
&mut anactrl,
|
||||
&mut pmc,
|
||||
&mut syscon,
|
||||
&mut _delay_timer,
|
||||
clocks.support_usbhs_token().unwrap(),
|
||||
),
|
||||
);
|
||||
#[cfg(feature = "usbfs")]
|
||||
let (usb_speed, usb_peripheral) = (
|
||||
UsbSpeed::Full,
|
||||
hal.usbfs.enabled_as_device(
|
||||
&mut anactrl,
|
||||
&mut pmc,
|
||||
&mut syscon,
|
||||
clocks.support_usbfs_token().unwrap(),
|
||||
),
|
||||
);
|
||||
|
||||
let usb_bus = UsbBus::new(usb_peripheral, usb0_vbus_pin);
|
||||
|
||||
defmt::debug!("codec init");
|
||||
wm8904::init_codec(&mut i2c_bus);
|
||||
|
||||
defmt::debug!("dma init");
|
||||
let i2s_dma_addr = &i2s_peripheral.i2s.fifowr as *const _ as *mut u32;
|
||||
let dma = DmaRing::<32, SLOT_SIZE_BYTES>::new(hal.dma.release(), &mut syscon, i2s_dma_addr, 4)
|
||||
.unwrap();
|
||||
let dma_ref = DMA_RING.init(dma);
|
||||
unsafe { DMA_RING_REF = Some(dma_ref) };
|
||||
|
||||
let mut clock = Clock {};
|
||||
let mut audio = Audio {
|
||||
i2s: i2s_peripheral,
|
||||
dma: dma_ring(),
|
||||
running: AtomicBool::new(false),
|
||||
};
|
||||
defmt::debug!("usb init");
|
||||
let config = AudioClassConfig::new(usb_speed, FunctionCode::Other, &mut clock, &mut audio)
|
||||
.with_output_config(TerminalConfig::new(
|
||||
4,
|
||||
1,
|
||||
2,
|
||||
FormatType1 {
|
||||
bit_resolution: 32,
|
||||
bytes_per_sample: 4,
|
||||
},
|
||||
TerminalType::ExtLineConnector,
|
||||
ChannelConfig::default_chans(2),
|
||||
IsochronousSynchronizationType::Asynchronous,
|
||||
LockDelay::Milliseconds(10),
|
||||
None,
|
||||
));
|
||||
|
||||
let mut uac2 = config.build(&usb_bus).unwrap();
|
||||
|
||||
let mut usb_dev = UsbDeviceBuilder::new(&usb_bus, UsbVidPid(0x1209, 0xcc1d))
|
||||
.composite_with_iads()
|
||||
.strings(&[StringDescriptors::default()
|
||||
.manufacturer("Generic")
|
||||
.product("usbd_uac2 device")
|
||||
.serial_number("123456789")])
|
||||
.unwrap()
|
||||
.max_packet_size_0(64)
|
||||
.unwrap()
|
||||
.device_class(0xef)
|
||||
.device_sub_class(0x02)
|
||||
.device_protocol(0x01)
|
||||
.build();
|
||||
|
||||
defmt::info!("main loop");
|
||||
|
||||
loop {
|
||||
usb_dev.poll(&mut [&mut uac2]);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,110 @@
|
||||
use cortex_m::prelude::{_embedded_hal_blocking_i2c_Write, _embedded_hal_blocking_i2c_WriteRead};
|
||||
use defmt::warn;
|
||||
|
||||
use crate::{BYTES_PER_FRAME, CODEC_I2C_ADDR, MCLK_FREQ, SAMPLE_RATE};
|
||||
|
||||
// copied from NXP SDK WM8904_Init
|
||||
pub(crate) fn init_codec<T>(i2c: &mut T)
|
||||
where
|
||||
T: _embedded_hal_blocking_i2c_WriteRead + _embedded_hal_blocking_i2c_Write,
|
||||
{
|
||||
let mut buf = [0u8; 2];
|
||||
match i2c.write_read(CODEC_I2C_ADDR, &[0], &mut buf) {
|
||||
Ok(_) => {
|
||||
let chip_id = ((buf[0] as u16) << 8) | buf[1] as u16;
|
||||
defmt::info!("Read chip ID: {:x}", chip_id)
|
||||
}
|
||||
Err(_) => defmt::error!("Error reading I2C"),
|
||||
}
|
||||
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x16, 0x00, 0x0f]).ok(); // clock rates 2 = OPCLK_ENA | CLK_SYS_ENA | CLK_DSP_ENA | TOCLK_ENA
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x6c, 0x01, 0x00]).ok(); // write sequencer 0 ENA
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x6f, 0x01, 0x00]).ok(); // write sequencer 3 START, INDEX=0
|
||||
// wait on write sequencer
|
||||
defmt::debug!("[codec] waiting on write seq");
|
||||
loop {
|
||||
let mut buf = [0; 2];
|
||||
i2c.write_read(CODEC_I2C_ADDR, &[0x70], &mut buf).ok();
|
||||
if buf[1] & 1 == 0 {
|
||||
break;
|
||||
}
|
||||
}
|
||||
defmt::debug!("[codec] write seq done");
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x14, 0x00, 0x00]).ok(); // clock rates 0
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x0c, 0x00, 0x00]).ok(); // power management 0 = IN PGAs disabled
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x0e, 0x00, 0x03]).ok(); // power management 2 = HPL_PGA_ENA | HPR_PGA_ENA
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x0f, 0x00, 0x00]).ok(); // power management 3 = line outs disabled
|
||||
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x12, 0x00, 0x0c]).ok(); // power management 6 = DACL_ENA | DACR_ENA
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x0a, 0x00, 0x00]).ok(); // analog adc 0 = ADC_OSR128
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x18, 0x00, 0x50]).ok(); // audio if 0 = AIFADCR_SRC | AIFDACR_SRC
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x21, 0x00, 0x40]).ok(); // dac digital 1 = DAC_OSR128
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x2c, 0x00, 0x05]).ok(); // analog lin 0 = 0dB (unmute)
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x2d, 0x00, 0x05]).ok(); // analog rin 0 = 0dB (unmute)
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x39, 0x00, 0x39]).ok(); // analog out1 left = vol=0dB
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x3a, 0x00, 0x39]).ok(); // analog out1 right = vol=0dB
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x3b, 0x00, 0x39]).ok(); // analog out2 left = vol=0dB
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x3c, 0x00, 0x39]).ok(); // analog out2 right = vol=0dB
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x43, 0x00, 0x03]).ok(); // dc server 0 = HPOUTL_ENA | HPOUTR_ENA
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x5a, 0x00, 0xff]).ok(); // analog hp 0 = remove all shorts etc
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x5e, 0x00, 0xff]).ok(); // analog lineout 0 = remove all shorts etc
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x68, 0x00, 0x01]).ok(); // enable class w charge pump
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x62, 0x00, 0x01]).ok(); // enable charge pump
|
||||
let aif_wl = match BYTES_PER_FRAME {
|
||||
4 => 0, // 16 bits per sample
|
||||
8 => 3, // 32 bits per sample
|
||||
_ => {
|
||||
warn!("only handling 16 or 32 bit samples for now");
|
||||
8
|
||||
}
|
||||
};
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x19, 0x00, (aif_wl << 2) | 2])
|
||||
.ok(); // audio if 1 = i2s, aif_wl
|
||||
|
||||
// Calculate sysclk vs. fs ratio. SYSCLK = MCLK
|
||||
let fs_ratio = MCLK_FREQ / SAMPLE_RATE;
|
||||
if !MCLK_FREQ.is_multiple_of(SAMPLE_RATE) {
|
||||
warn!("sample rate should be a multiple of mclk")
|
||||
}
|
||||
let clk_sys_rate: u16 = match fs_ratio {
|
||||
64 => 0,
|
||||
128 => 1,
|
||||
192 => 2,
|
||||
256 => 3,
|
||||
384 => 4,
|
||||
512 => 5,
|
||||
768 => 6,
|
||||
1024 => 7,
|
||||
1408 => 8,
|
||||
1536 => 9,
|
||||
_ => {
|
||||
warn!("unsupport ratio {}", fs_ratio);
|
||||
0
|
||||
}
|
||||
};
|
||||
let sample_rate: u16 = match SAMPLE_RATE {
|
||||
r if r < 11025 => 0, // 0-11024
|
||||
r if r < 16000 => 1, // 11025 - 15999
|
||||
r if r < 22050 => 2, // 16000 - 22049
|
||||
r if r < 32000 => 3, // 22050 - 31999
|
||||
r if r < 44100 => 4, // 32000 - 44099
|
||||
_ => 5, // 44100+
|
||||
};
|
||||
let clock_rates_1 = ((clk_sys_rate << 10) | sample_rate).to_be_bytes();
|
||||
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x15, clock_rates_1[0], clock_rates_1[1]])
|
||||
.ok(); // sys clock rate 512fs, sample rate 48
|
||||
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x16, 0x00, 0x0f]).ok(); // clock rates 2 = CLK_SYS_ENA
|
||||
|
||||
// Calculate bclk_div
|
||||
let bits_per_frame = BYTES_PER_FRAME * 8;
|
||||
let bits_per_second = bits_per_frame as u32 * SAMPLE_RATE;
|
||||
let bclk_div = MCLK_FREQ / bits_per_second;
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x1a, 0x00, bclk_div as u8])
|
||||
.ok(); // audio interface 2 = no gpio, bclk_div
|
||||
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x1b, 0x00, 0x00]).ok(); // audio interface 3 = input lrclock
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x3d, 0x00, 0x00]).ok(); // analog out12 zc = play source = dac
|
||||
i2c.write(CODEC_I2C_ADDR, &[0x1e, 0x01, 0xff]).ok(); // dac vol left = update left/right = 0dB
|
||||
}
|
||||
Reference in New Issue
Block a user