361 lines
10 KiB
Rust
361 lines
10 KiB
Rust
//! Contains hardware setup unrelated to Usb Audio Class implementation
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use crate::Syscon;
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use crate::hal;
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use crate::{MCLK_FREQ, SAMPLE_RATE, pac};
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use core::cell::UnsafeCell;
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use core::mem::MaybeUninit;
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use defmt::debug;
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use hal::{
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Enabled, Iocon, Pin,
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drivers::pins,
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peripherals::syscon::{ClockControl, ResetControl},
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traits::wg::digital::v2::{OutputPin, ToggleableOutputPin},
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typestates::pin::{gpio::direction::Output, state::Gpio},
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};
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pub(crate) struct PllConstants {
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pub m: u16, // 1-65535
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pub n: u8, // 1-255
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pub p: u8, // 1-31
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pub selp: u8, // 5 bits
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pub seli: u8, // 6 bits
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}
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impl PllConstants {
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pub(crate) const fn new(n: u8, m: u16, p: u8) -> Self {
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assert!(n != 0, "1 <= N <= 255");
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assert!(m != 0, "1 <= M <= 65535");
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assert!(p != 0 && p <= 31, "1 <= P <= 31");
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// Following ripped from lpc55-hal and made const
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// UM 4.6.6.3.2
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let selp = {
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let v = (m >> 2) + 1;
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if v < 31 { v } else { 31 }
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} as u8;
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let seli = {
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let v = match m {
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m if m >= 8000 => 1,
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m if m >= 122 => 8000 / m,
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_ => 2 * (m >> 2) + 3,
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};
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if v < 63 { v } else { 63 }
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} as u8;
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// let seli = min(2*(m >> 2) + 3, 63);
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Self {
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n,
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m,
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p,
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selp,
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seli,
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}
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}
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}
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impl defmt::Format for PllConstants {
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fn format(&self, fmt: defmt::Formatter) {
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let factor = f32::from(self.m) / (f32::from(self.n) * 2.0 * f32::from(self.p));
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defmt::write!(
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fmt,
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"m: {} n: {} p: {} selp: {} seli: {} fout: fin * {}",
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self.m,
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self.n,
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self.p,
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self.selp,
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self.seli,
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factor
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);
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}
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}
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// Fo = M/(N*2*P) * Fin
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// Fo = 3072/(125*2*8) * 16MHz = 24.576MHz
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const AUDIO_PLL: PllConstants = PllConstants::new(125, 3072, 8);
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// Set PLL0 to 24.576MHz, start, and wait for lock
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// This is not exposed by lpc55-hal, unfortunately. Copy their implementation here.
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pub(crate) fn init_audio_pll() {
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let syscon = unsafe { &*pac::SYSCON::ptr() };
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let pmc = unsafe { &*pac::PMC::ptr() };
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let anactrl = unsafe { &*pac::ANACTRL::ptr() };
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debug!("start clk_in");
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pmc.pdruncfg0
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.modify(|_, w| w.pden_xtal32m().poweredon().pden_ldoxo32m().poweredon());
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syscon.clock_ctrl.modify(|_, w| w.clkin_ena().enable());
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anactrl
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.xo32m_ctrl
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.modify(|_, w| w.enable_system_clk_out().enable());
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debug!("init pll0: {}", AUDIO_PLL);
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pmc.pdruncfg0
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.modify(|_, w| w.pden_pll0().poweredoff().pden_pll0_sscg().poweredoff());
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syscon.pll0clksel.write(|w| w.sel().enum_0x1()); // clk_in
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syscon.pll0ctrl.write(|w| unsafe {
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w.clken()
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.enable()
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.seli()
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.bits(AUDIO_PLL.seli)
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.selp()
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.bits(AUDIO_PLL.selp)
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});
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syscon
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.pll0ndec
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.write(|w| unsafe { w.ndiv().bits(AUDIO_PLL.n) });
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syscon.pll0ndec.write(|w| unsafe {
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w.ndiv().bits(AUDIO_PLL.n).nreq().set_bit() // latch
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});
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syscon
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.pll0pdec
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.write(|w| unsafe { w.pdiv().bits(AUDIO_PLL.p) });
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syscon.pll0pdec.write(|w| unsafe {
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w.pdiv().bits(AUDIO_PLL.p).preq().set_bit() // latch
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});
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syscon.pll0sscg0.write(|w| unsafe { w.md_lbs().bits(0) });
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syscon
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.pll0sscg1
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.write(|w| unsafe { w.mdiv_ext().bits(AUDIO_PLL.m).sel_ext().set_bit() });
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syscon.pll0sscg1.write(|w| unsafe {
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w.mdiv_ext()
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.bits(AUDIO_PLL.m)
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.sel_ext()
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.set_bit()
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.mreq()
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.set_bit() // latch
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.md_req()
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.set_bit() // latch
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});
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pmc.pdruncfg0
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.modify(|_, w| w.pden_pll0().poweredon().pden_pll0_sscg().poweredon());
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debug!("pll0 wait for lock");
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let mut i = 0usize;
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while syscon.pll0stat.read().lock().bit_is_clear() {
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i += 1;
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}
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debug!("pll0 locked after {} tries", i);
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}
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pub struct I2sHandles {
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pub tx: pac::I2S7,
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pub rx: pac::I2S6,
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}
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pub fn init_i2s(
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fc7: pac::FLEXCOMM7,
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i2s7: pac::I2S7,
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fc6: pac::FLEXCOMM6,
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i2s6: pac::I2S6,
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syscon: &mut Syscon,
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) -> I2sHandles {
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defmt::debug!("init i2s");
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// Enable BOTH
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fc7.clear_reset(syscon);
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fc7.enable_clock(syscon);
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fc6.clear_reset(syscon);
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fc6.enable_clock(syscon);
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{
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let sc = unsafe { pac::SYSCON::ptr().as_ref().unwrap() };
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let ioc = unsafe { pac::IOCON::ptr().as_ref().unwrap() };
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// MCLK source
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//
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sc.mclkclksel.write(|w| w.sel().enum_0x1()); // PLL0
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// MCLK div
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sc.mclkdiv
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.write(|w| unsafe { w.div().bits(1).halt().run().reset().released() }); // div by 2 = PLL0 fout / 2 = 12.288MHz, max for WM8904 @ 96k
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// MCLK out config
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ioc.pio1_31.modify(|_, w| {
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w.func()
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.alt1()
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.mode()
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.inactive()
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.slew()
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.fast()
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.invert()
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.disabled()
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.digimode()
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.digital()
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.od()
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.normal()
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});
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// FC7 clock
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sc.fcclksel7().modify(|_, w| w.sel().enum_0x5()); // MCLK
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// FC6 clock
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sc.fcclksel6().modify(|_, w| w.sel().enum_0x5()); // MCLK
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// MCLK out
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sc.mclkio.modify(|_, w| w.mclkio().output());
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// Enable clock for sysctl, it's not mapped into Peripherals
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sc.ahbclkctrlset[2].write(|w| unsafe { w.bits(1 << 15) });
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while sc.ahbclkctrl2.read().sysctl().is_disable() {}
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let sysctrl = unsafe { pac::SYSCTL::ptr().as_ref().unwrap() };
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sysctrl.sharedctrlset[0].write(|w| w.sharedscksel().flexcomm7().sharedwssel().flexcomm7()); // FC7 drives shared SCK, WS
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sysctrl.fcctrlsel[7].write(|w| {
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w.sckinsel()
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.shared_set0_i2s_signals()
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.wsinsel()
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.shared_set0_i2s_signals()
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}); // FC7 uses shared set
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sysctrl.fcctrlsel[6].write(|w| {
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w.sckinsel()
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.shared_set0_i2s_signals()
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.wsinsel()
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.shared_set0_i2s_signals()
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});
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// for _ in 0..1000 {
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// cortex_m::asm::nop();
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// }
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}
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// Select I2S TX function
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fc7.pselid.write(|w| w.persel().i2s_transmit());
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// Select I2S RX function
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fc6.pselid.write(|w| w.persel().i2s_receive());
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let out_regs = i2s7;
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let in_regs = i2s6;
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// Enable TX FIFO only
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out_regs.fifocfg.write(|w| {
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w.enabletx()
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.enabled()
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.txi2se0() // transmit 0s when empty - only supported option for 32b data
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.zero()
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.emptytx() // reset the tx queue
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.set_bit()
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});
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out_regs
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.cfg2
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.write(|w| unsafe { w.position().bits(0).framelen().bits(63) }); // framelen = 64
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let bclk_div = (MCLK_FREQ / SAMPLE_RATE / 64) as u16;
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out_regs
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.div
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.write(|w| unsafe { w.div().bits(bclk_div - 1) }); // Clock source is MCLK (12.288MHz) / 4 = 3MHz
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// TX Config
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out_regs.cfg1.write(|w| unsafe {
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w.mstslvcfg()
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.normal_master()
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.onechannel()
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.dual_channel()
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.datalen()
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.bits(31)
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.mainenable()
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.enabled()
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.mode()
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.classic_mode()
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.datapause()
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.normal()
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});
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// Enable RX FIFO only
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in_regs
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.fifocfg
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.write(|w| w.enablerx().enabled().emptyrx().set_bit());
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in_regs
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.cfg2
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.write(|w| unsafe { w.position().bits(0).framelen().bits(63) }); // framelen = 64
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in_regs.div.write(|w| unsafe { w.div().bits(0) });
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in_regs.cfg1.write(|w| unsafe {
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w.mstslvcfg()
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.normal_slave_mode()
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.onechannel()
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.dual_channel()
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.datalen()
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.bits(31)
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.mainenable()
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.enabled()
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.mode()
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.classic_mode()
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.datapause()
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.normal()
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});
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I2sHandles {
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tx: out_regs,
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rx: in_regs,
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}
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}
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pub struct SharedLed<T: OutputPin> {
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inner: UnsafeCell<T>,
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}
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unsafe impl<T: OutputPin> Sync for SharedLed<T> {}
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impl<T: OutputPin> SharedLed<T> {
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pub fn new(inner: T) -> Self {
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Self {
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inner: UnsafeCell::new(inner),
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}
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}
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pub fn on(&self) {
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unsafe {
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(*self.inner.get()).set_low().ok();
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}
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}
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pub fn off(&self) {
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unsafe {
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(*self.inner.get()).set_high().ok();
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}
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}
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}
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impl<T: OutputPin + ToggleableOutputPin> SharedLed<T> {
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pub fn toggle(&self) {
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unsafe {
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(*self.inner.get()).toggle().ok();
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}
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}
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}
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type RedLed = Pin<pins::Pio1_6, Gpio<Output>>;
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type GreenLed = Pin<pins::Pio1_7, Gpio<Output>>;
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type BlueLed = Pin<pins::Pio1_4, Gpio<Output>>;
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pub static RED_LED: MaybeUninit<SharedLed<RedLed>> = MaybeUninit::uninit();
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pub static GREEN_LED: MaybeUninit<SharedLed<GreenLed>> = MaybeUninit::uninit();
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pub static BLUE_LED: MaybeUninit<SharedLed<BlueLed>> = MaybeUninit::uninit();
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pub fn init_leds(iocon: &mut Iocon<Enabled>, gpio: &mut hal::Gpio<Enabled>) {
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let red_led = SharedLed::new(
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pins::Pio1_6::take()
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.unwrap()
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.into_gpio_pin(iocon, gpio)
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.into_output_low(),
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);
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let green_led = SharedLed::new(
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pins::Pio1_7::take()
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.unwrap()
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.into_gpio_pin(iocon, gpio)
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.into_output_low(),
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);
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let blue_led = SharedLed::new(
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pins::Pio1_4::take()
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.unwrap()
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.into_gpio_pin(iocon, gpio)
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.into_output_low(),
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);
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unsafe {
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core::ptr::write(RED_LED.as_ptr() as *mut SharedLed<RedLed>, red_led);
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core::ptr::write(GREEN_LED.as_ptr() as *mut SharedLed<GreenLed>, green_led);
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core::ptr::write(BLUE_LED.as_ptr() as *mut SharedLed<BlueLed>, blue_led);
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}
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}
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pub fn red_led() -> &'static SharedLed<RedLed> {
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unsafe { &*RED_LED.as_ptr() }
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}
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pub fn green_led() -> &'static SharedLed<GreenLed> {
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unsafe { &*GREEN_LED.as_ptr() }
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}
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pub fn blue_led() -> &'static SharedLed<BlueLed> {
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unsafe { &*BLUE_LED.as_ptr() }
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}
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