much progress, descriptors and sample rates getting basically working?

This commit is contained in:
2026-04-23 14:38:28 -07:00
parent ac6618a162
commit 539e0aab98
16 changed files with 1435 additions and 533 deletions
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checksum = "98816b1accafbb09085168b90f27e93d790b4bfa19d883466b5e53315b5f06a6"
dependencies = [
"defmt 0.3.100",
"heapless 0.8.0",
"portable-atomic",
]
[[package]]
name = "usbd-uac2"
version = "0.1.0"
dependencies = [
"byteorder-embedded-io",
"defmt 1.0.1",
"embedded-io",
"modular-bitfield",
"num-traits",
"usb-device",
]
[[package]]
name = "vcell"
version = "0.1.3"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "77439c1b53d2303b20d9459b1ade71a83c716e3f9c34f3228c00e6f185d6c002"
[[package]]
name = "version_check"
version = "0.9.5"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "0b928f33d975fc6ad9f86c8f283853ad26bdd5b10b7f1542aa2fa15e2289105a"
[[package]]
name = "void"
version = "1.0.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "6a02e4885ed3bc0f2de90ea6dd45ebcbb66dacffe03547fadbb0eeae2770887d"
[[package]]
name = "volatile-register"
version = "0.2.2"
source = "registry+https://github.com/rust-lang/crates.io-index"
checksum = "de437e2a6208b014ab52972a27e59b33fa2920d3e00fe05026167a1c509d19cc"
dependencies = [
"vcell",
]
+25
View File
@@ -0,0 +1,25 @@
[package]
name = "lpc55s28-evk"
version = "0.1.0"
edition = "2024"
[dependencies]
cortex-m = { version = "0.7.7", features = ["critical-section-single-core"] }
cortex-m-rt = "0.7.5"
defmt = "1.0.1"
defmt-rtt = "1.1.0"
embedded-hal = "1.0.0"
embedded-io = "0.7.1"
log-to-defmt = "0.1.0"
lpc55-hal = { version = "0.5.0", path = "../lpc55-hal" }
nb = "1.1.0"
panic-halt = "1.0.0"
static_cell = "2.1.1"
usb-device = "0.3"
usbd-uac2 = { version = "0.1.0", path = "../..", features = ["defmt"]}
[profile.release]
opt-level = "z"
lto = true
debug = true
codegen-units = 1
+9
View File
@@ -0,0 +1,9 @@
[default.general]
chip = "LPC55S28JBD100"
[default.rtt]
enabled = true
[default.gdb]
enabled = true
[debug.rtt]
enabled = false
+26
View File
@@ -0,0 +1,26 @@
MEMORY
{
FLASH : ORIGIN = 0x00000000, LENGTH = 512K
/* for use with standard link.x */
RAM : ORIGIN = 0x20000000, LENGTH = 64K
/* would be used with proper link.x */
/* needs changes to r0 (initialization code) */
/* SRAM0 : ORIGIN = 0x20000000, LENGTH = 64K */
/* SRAM1 : ORIGIN = 0x20010000, LENGTH = 64K */
/* SRAM2 : ORIGIN = 0x20020000, LENGTH = 64K */
/* SRAM3 : ORIGIN = 0x20030000, LENGTH = 64K */
/* CASPER SRAM regions */
/* SRAMX0: ORIGIN = 0x1400_0000, LENGTH = 4K /1* to 0x1400_0FFF *1/ */
/* SRAMX1: ORIGIN = 0x1400_4000, LENGTH = 4K /1* to 0x1400_4FFF *1/ */
/* USB1 SRAM regin */
/* USB1_SRAM : ORIGIN = 0x40100000, LENGTH = 16K */
/* To define our own USB RAM section in one regular */
/* RAM, probably easiest to shorten length of RAM */
/* above, and use this freed RAM section */
}
+258
View File
@@ -0,0 +1,258 @@
#![no_main]
#![no_std]
// extern crate panic_semihosting;
extern crate panic_halt;
use core::cell::OnceCell;
use cortex_m::asm::delay;
use cortex_m_rt::entry;
use embedded_io::{ErrorType, Write};
use nb;
#[allow(unused_imports)]
use hal::prelude::*;
#[allow(unused_imports)]
use lpc55_hal as hal;
use lpc55_hal::{
drivers::{
Serial,
pins::{PinId, Pio0_29, Pio0_30},
serial::Tx,
},
peripherals::flexcomm::Usart0,
typestates::pin::{
flexcomm::{Usart, UsartPins},
function::{FC0_RXD_SDA_MOSI_DATA, FC0_TXD_SCL_MISO_WS},
state::Special,
},
};
use core::convert::Infallible;
use defmt;
use defmt_rtt as _;
use hal::drivers::{Timer, UsbBus, pins};
use static_cell::StaticCell;
use usb_device::{
bus,
device::{StringDescriptors, UsbDeviceBuilder, UsbVidPid},
endpoint::IsochronousSynchronizationType,
};
use usbd_uac2::{
self, AudioClassConfig, RangeEntry, TerminalConfig, USB_CLASS_AUDIO, UsbAudioClass,
UsbAudioClockImpl, UsbSpeed,
constants::{FunctionCode, TerminalType},
descriptors::{ChannelConfig, ClockSource, ClockType, FormatType1, LockDelay},
};
type SERIAL_RX_PIN = hal::Pin<Pio0_29, Special<FC0_RXD_SDA_MOSI_DATA>>;
type SERIAL_TX_PIN = hal::Pin<Pio0_30, Special<FC0_TXD_SCL_MISO_WS>>;
type SERIAL_PINS = (SERIAL_TX_PIN, SERIAL_RX_PIN);
static SERIAL: StaticCell<DefmtUart<Usart0>> = StaticCell::new();
pub struct DefmtUart<U>(pub Tx<U>)
where
U: Usart;
impl<U> ErrorType for DefmtUart<U>
where
U: Usart,
{
type Error = Infallible;
}
impl<U> Write for DefmtUart<U>
where
U: Usart,
{
fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
buf.iter().map(|c| nb::block!(self.0.write(*c))).last();
Ok(buf.len())
}
fn flush(&mut self) -> Result<(), Self::Error> {
// Blocking write, so flush is a no-op
Ok(())
}
}
struct Clock {}
impl Clock {
const RATES: [RangeEntry<u32>; 1] = [RangeEntry::new_fixed(44100)];
}
impl UsbAudioClockImpl for Clock {
const CLOCK_TYPE: usbd_uac2::descriptors::ClockType = ClockType::InternalFixed;
const SOF_SYNC: bool = false;
fn get_sample_rate(&self) -> core::result::Result<u32, usbd_uac2::UsbAudioClassError> {
Ok(Clock::RATES[0].min)
}
fn get_rates(
&self,
) -> core::result::Result<&[usbd_uac2::RangeEntry<u32>], usbd_uac2::UsbAudioClassError> {
Ok(&Clock::RATES)
}
}
struct Audio {}
impl<'a, B: bus::UsbBus> UsbAudioClass<'a, B> for Audio {}
#[entry]
fn main() -> ! {
let hal = hal::new();
let mut anactrl = hal.anactrl;
let mut pmc = hal.pmc;
let mut syscon = hal.syscon;
let mut gpio = hal.gpio.enabled(&mut syscon);
let mut iocon = hal.iocon.enabled(&mut syscon);
let mut red_led = pins::Pio1_6::take()
.unwrap()
.into_gpio_pin(&mut iocon, &mut gpio)
.into_output(hal::drivers::pins::Level::Low); // start turned on
let usb0_vbus_pin = pins::Pio0_22::take()
.unwrap()
.into_usb0_vbus_pin(&mut iocon);
let serial_rx_pin = pins::Pio0_29::take()
.unwrap()
.into_usart0_rx_pin(&mut iocon);
let serial_tx_pin = pins::Pio0_30::take()
.unwrap()
.into_usart0_tx_pin(&mut iocon);
iocon.disabled(&mut syscon).release(); // save the environment :)
let clocks = hal::ClockRequirements::default()
// .system_frequency(24.mhz())
// .system_frequency(72.mhz())
.system_frequency(96.MHz())
.configure(&mut anactrl, &mut pmc, &mut syscon)
.unwrap();
let mut _delay_timer = Timer::new(
hal.ctimer
.0
.enabled(&mut syscon, clocks.support_1mhz_fro_token().unwrap()),
);
let usart = hal
.flexcomm
.0
.enabled_as_usart(&mut syscon, &clocks.support_flexcomm_token().unwrap());
let serial_config = hal::drivers::serial::config::Config::default().speed(115_200.Hz());
let serial = Serial::new(usart, (serial_tx_pin, serial_rx_pin), serial_config).split();
let serial_tx = DefmtUart(serial.0);
// defmt_serial::defmt_serial(SERIAL.init(serial_tx));
let usb_peripheral = hal.usbhs.enabled_as_device(
&mut anactrl,
&mut pmc,
&mut syscon,
&mut _delay_timer,
clocks.support_usbhs_token().unwrap(),
);
let usb_bus = UsbBus::new(usb_peripheral, usb0_vbus_pin);
let clock = Clock {};
let audio = Audio {};
let config = AudioClassConfig::new(UsbSpeed::High, FunctionCode::Other, &clock, &audio)
.with_input_config(TerminalConfig::new(
2,
1,
2,
FormatType1 {
bit_resolution: 24,
bytes_per_sample: 4,
},
TerminalType::ExtLineConnector,
ChannelConfig::default_chans(2),
IsochronousSynchronizationType::Adaptive,
LockDelay::Milliseconds(10),
None,
))
.with_output_config(TerminalConfig::new(
4,
1,
2,
FormatType1 {
bit_resolution: 24,
bytes_per_sample: 4,
},
TerminalType::ExtLineConnector,
ChannelConfig::default_chans(2),
IsochronousSynchronizationType::Adaptive,
LockDelay::Milliseconds(10),
None,
));
let mut uac2 = config.build(&usb_bus).unwrap();
let mut usb_dev = UsbDeviceBuilder::new(&usb_bus, UsbVidPid(0x1209, 0xcc1d))
.composite_with_iads()
.strings(&[StringDescriptors::default()
.manufacturer("VE7XEN")
.product("Guac")
.serial_number("123456789")])
.unwrap()
.max_packet_size_0(64)
.unwrap()
.device_class(0xef)
.device_sub_class(0x02)
.device_protocol(0x01)
.build();
defmt::info!("main loop");
let mut need_zlp = false;
let mut buf = [0u8; 8];
let mut size = 0;
let mut buf_in_use = false;
loop {
// if !usb_dev.poll(&mut []) {
// if !usb_dev.poll(&mut [&mut serial]) {
if !usb_dev.poll(&mut [&mut uac2]) {
continue;
}
// let mut buf = [0u8; 512];
// match serial.read(&mut buf) {
// Ok(count) if count > 0 => {
// assert!(count == 1);
// // hprintln!("received some data on the serial port: {:?}", &buf[..count]).ok();
// // cortex_m_semihosting::hprintln!("received:\n{}", core::str::from_utf8(&buf[..count]).unwrap()).ok();
// red_led.set_low().ok(); // Turn on
// // cortex_m_semihosting::hprintln!("read {:?}", &buf[..count]).ok();
// cortex_m_semihosting::hprintln!("read {:?}", count).ok();
// // Echo back in upper case
// for c in buf[0..count].iter_mut() {
// if (0x61 <= *c && *c <= 0x7a) || (0x41 <= *c && *c <= 0x5a) {
// *c ^= 0x20;
// }
// }
// let mut write_offset = 0;
// while write_offset < count {
// match serial.write(&buf[write_offset..count]) {
// Ok(len) if len > 0 => {
// write_offset += len;
// cortex_m_semihosting::hprintln!("wrote {:?}", len).ok();
// },
// _ => {},
// }
// }
// // hprintln!("wrote it back").ok();
// }
// _ => {}
// }
red_led.set_high().ok(); // Turn off
}
}