Merge branch 'evk'
This commit is contained in:
@@ -0,0 +1,253 @@
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use crate::{CodecPins, traits::Dac};
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use embedded_hal::prelude::{
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_embedded_hal_blocking_i2c_Write, _embedded_hal_blocking_i2c_WriteRead,
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};
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const WM8904_I2C_ADDRESS: u8 = 0b0011010;
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const MCLK: u32 = 24576000 / 2; // assume EVK TODO: better
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#[repr(u8)]
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#[derive(Clone, Copy)]
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#[allow(dead_code)]
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enum RegisterAddress {
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SwResetId = 0x00,
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BiasControl0 = 0x04,
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VmidControl = 0x05,
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MicBiasControl0 = 0x06,
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MicBiasControl1 = 0x07,
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AnaAdc0 = 0x0a,
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PowerMgmt0 = 0x0c,
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PowerMgmt2 = 0x0e,
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PowerMgmt3 = 0x0f,
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PowerMgmt6 = 0x12,
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ClockRates0 = 0x14,
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ClockRates1 = 0x15,
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ClockRates2 = 0x16,
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AudioInterface0 = 0x18,
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AudioInterface1 = 0x19,
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AudioInterface2 = 0x1a,
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AudioInterface3 = 0x1b,
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DacDigiVolLeft = 0x1e,
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DacDigiVolRight = 0x1f,
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DacDigital0 = 0x20,
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DacDigi1 = 0x21,
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AdcDigiVolLeft = 0x24,
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AdcDigiVolRight = 0x25,
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AdcDigital0 = 0x26,
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DigiMic0 = 0x27,
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Drc0 = 0x28,
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Drc1 = 0x29,
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Drc2 = 0x2a,
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Drc3 = 0x2b,
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AnaLeftIn0 = 0x2c,
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AnaRightIn0 = 0x2d,
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AnaLeftIn1 = 0x2e,
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AnaRightIn1 = 0x2f,
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AnaOut1Left = 0x39,
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AnaOut1Right = 0x3a,
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AnaOut2Left = 0x3b,
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AnaOut2Right = 0x3c,
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AnaOut12Zc = 0x3d,
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DcServo0 = 0x43,
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DcServo1 = 0x44,
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DcServo2 = 0x45,
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DcServo4 = 0x47,
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DcServo5 = 0x48,
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DcServo6 = 0x49,
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DcServo7 = 0x4a,
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DcServo8 = 0x4b,
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DcServo9 = 0x4c,
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DcServoRb0 = 0x4d,
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AnaHp0 = 0x5a,
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AnaLineOut0 = 0x5e,
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ChargePump0 = 0x62,
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ClassW = 0x68,
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WriteSeq0 = 0x6c,
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WriteSeq1 = 0x6d,
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WriteSeq2 = 0x6e,
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WriteSeq3 = 0x6f,
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WriteSeq4 = 0x70,
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FllControl1 = 0x74,
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FllControl2 = 0x75,
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FllControl3 = 0x76,
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FllControl4 = 0x77,
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FllControl5 = 0x78,
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GpioControl1 = 0x79,
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GpioControl2 = 0x7a,
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GpioControl3 = 0x7b,
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GpioControl4 = 0x7c,
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DigiPulls = 0x7e,
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IntStatus = 0x7f,
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IntStatusMask = 0x80,
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IntPriority = 0x81,
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IntDebounce = 0x82,
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Eq1 = 0x86,
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Eq2 = 0x87,
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Eq3 = 0x88,
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Eq4 = 0x89,
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Eq5 = 0x8a,
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Eq6 = 0x8b,
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Eq7 = 0x8c,
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Eq8 = 0x8d,
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Eq9 = 0x8e,
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Eq10 = 0x8f,
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Eq11 = 0x90,
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Eq12 = 0x91,
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Eq13 = 0x92,
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Eq14 = 0x93,
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Eq15 = 0x94,
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Eq16 = 0x95,
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Eq17 = 0x96,
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Eq18 = 0x97,
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Eq19 = 0x98,
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Eq20 = 0x99,
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Eq21 = 0x9a,
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Eq22 = 0x9b,
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Eq23 = 0x9c,
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Eq24 = 0x9d,
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AdcTest0 = 0xc6,
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FllNcoTest0 = 0xf7,
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FllNcoTest1 = 0xf8,
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}
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pub struct Wm8904Dac<T> {
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i2c: T,
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pins: CodecPins,
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mclk: u32,
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}
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impl<T> Wm8904Dac<T>
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where
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T: _embedded_hal_blocking_i2c_WriteRead + _embedded_hal_blocking_i2c_Write,
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{
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#[inline]
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fn write_reg(&mut self, reg: RegisterAddress, val: u16) {
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let b = val.to_be_bytes();
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defmt::info!("i2c w [{:?}]", &[reg as u8, b[0], b[1]]);
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self.i2c
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.write(WM8904_I2C_ADDRESS, &[reg as u8, b[0], b[1]])
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.ok();
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}
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fn cr1_for_rate(&self, rate: u32) -> u16 {
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let fs_ratio = self.mclk / rate;
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if !self.mclk.is_multiple_of(rate) {
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defmt::warn!("sample rate should be a multiple of mclk");
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}
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let clk_sys_rate: u16 = match fs_ratio {
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64 => 0,
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128 => 1,
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192 => 2,
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256 => 3,
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384 => 4,
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512 => 5,
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768 => 6,
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1024 => 7,
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1408 => 8,
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1536 => 9,
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_ => {
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defmt::warn!("unsupport ratio {}", fs_ratio);
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0
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}
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};
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let sample_rate: u16 = match rate {
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r if r < 11025 => 0, // 0-11024
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r if r < 16000 => 1, // 11025 - 15999
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r if r < 22050 => 2, // 16000 - 22049
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r if r < 32000 => 3, // 22050 - 31999
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r if r < 44100 => 4, // 32000 - 44099
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_ => 5, // 44100+
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};
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(clk_sys_rate << 10) | sample_rate
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}
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fn blck_div_for_rate(&self, rate: u32) -> u16 {
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let bits_per_frame = 64;
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let bits_per_second = bits_per_frame * rate;
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(self.mclk / bits_per_second) as u16
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}
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}
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impl<T> Dac<T> for Wm8904Dac<T>
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where
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T: _embedded_hal_blocking_i2c_WriteRead + _embedded_hal_blocking_i2c_Write,
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{
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fn new(i2c: T, pins: CodecPins) -> Self {
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Self {
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i2c,
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pins,
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mclk: MCLK,
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}
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}
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fn init(&mut self) {
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let mut buf = [0u8; 2];
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match self.i2c.write_read(WM8904_I2C_ADDRESS, &[0], &mut buf) {
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Ok(_) => {
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let chip_id = ((buf[0] as u16) << 8) | buf[1] as u16;
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defmt::info!("Read chip ID: {:x}", chip_id)
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}
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Err(_) => defmt::error!("Error reading I2C"),
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}
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self.write_reg(RegisterAddress::ClockRates2, 0x000f); // OPCLK_ENA | CLK_SYS_ENA | CLK_DSP_ENA | TOCLK_ENA
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self.write_reg(RegisterAddress::WriteSeq0, 0x0100); // write sequencer 0 ENA
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self.write_reg(RegisterAddress::WriteSeq3, 0x0100); // write sequencer 3 START, INDEX=0
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// wait on write sequencer
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defmt::info!("[codec] waiting on write seq");
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loop {
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let mut buf = [0; 2];
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self.i2c
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.write_read(WM8904_I2C_ADDRESS, &[0x70], &mut buf)
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.ok();
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if buf[1] & 1 == 0 {
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break;
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}
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}
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defmt::debug!("[codec] write seq done");
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self.write_reg(RegisterAddress::ClockRates0, 0);
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self.write_reg(RegisterAddress::PowerMgmt0, 0); // IN PGAs disabled
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self.write_reg(RegisterAddress::PowerMgmt2, 0x0003); // HPL_PGA_ENA | HPR_PGA_ENA
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self.write_reg(RegisterAddress::PowerMgmt3, 0); //line outs disabled
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self.write_reg(RegisterAddress::PowerMgmt6, 0x000c); // power management 6 = DACL_ENA | DACR_ENA
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self.write_reg(RegisterAddress::AudioInterface0, 0x0050); // audio if 0 = AIFADCR_SRC | AIFDACR_SRC
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self.write_reg(RegisterAddress::DacDigi1, 0x0040); // dac digital 1 = DAC_OSR128
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self.write_reg(RegisterAddress::AnaLeftIn0, 0x0005);
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self.write_reg(RegisterAddress::AnaRightIn0, 0x0005);
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self.write_reg(RegisterAddress::AnaOut1Left, 0x0039); // analog out1 left = vol=0dB
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self.write_reg(RegisterAddress::AnaOut1Right, 0x0039); // analog out1 right = vol=0dB
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self.write_reg(RegisterAddress::AnaOut2Left, 0x0039); // analog out2 left = vol=0dB
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self.write_reg(RegisterAddress::AnaOut2Right, 0x0039); // analog out2 right = vol=0dB
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self.write_reg(RegisterAddress::DcServo0, 0x0003); // dc servo 0 = HPOUTL_ENA | HPOUTR_ENA
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self.write_reg(RegisterAddress::AnaHp0, 0x00ff); // analog hp 0 = remove all shorts etc
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self.write_reg(RegisterAddress::AnaLineOut0, 0x00ff); // analog lineout 0 = remove all shorts etc
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self.write_reg(RegisterAddress::ClassW, 0x0001); // enable class w charge pump
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self.write_reg(RegisterAddress::ChargePump0, 0x0001); // enable charge pump
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self.write_reg(RegisterAddress::AudioInterface1, (3 << 2) | 2); // audio if 1 = i2s, 32 bit per sample
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self.write_reg(RegisterAddress::ClockRates1, self.cr1_for_rate(96000)); // Set up for 48k, impl will change if needed
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self.write_reg(RegisterAddress::ClockRates2, 0x000f); // clock rates 2 = CLK_SYS_ENA
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self.write_reg(
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RegisterAddress::AudioInterface2,
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self.blck_div_for_rate(96000),
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);
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self.write_reg(RegisterAddress::AudioInterface3, 0); // audio interface 3 = input lrclock
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self.write_reg(RegisterAddress::AnaOut12Zc, 0); // analog out12 zc = play source = dac
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self.write_reg(RegisterAddress::DacDigiVolLeft, 0x01ff); // dac vol left = update left/right = 0dB
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}
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fn change_rate(&mut self, new_rate: u32) {
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// TODO: mute, stop clocks etc.
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defmt::info!("dac rate -> {}", new_rate);
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self.write_reg(RegisterAddress::ClockRates1, self.cr1_for_rate(new_rate));
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self.write_reg(
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RegisterAddress::AudioInterface2,
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self.blck_div_for_rate(new_rate),
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);
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}
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fn mute(&mut self) {
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// self.write_reg(RegisterAddress::DacDigiVolLeft, 0x0100);
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}
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fn unmute(&mut self) {
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// TODO: restore previous volume
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// self.write_reg(RegisterAddress::DacDigiVolLeft, 0x01ff);
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}
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}
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+73
-1
@@ -1,5 +1,5 @@
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use crate::pac;
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use defmt::debug;
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use defmt::{debug, info};
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pub(crate) struct PllConstants {
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pub m: u16, // 1-65535
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@@ -112,3 +112,75 @@ pub(crate) fn init_sys_pll1() {
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syscon.fmccr.modify(|_, w| w.flashtim().flashtim11());
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syscon.mainclkselb.modify(|_, w| w.sel().enum_0x2()); // pll1
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}
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||||
// Fo = M/(N*2*P) * Fin
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// Fo = 3072/(125*2*8) * 16MHz = 24.576MHz
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||||
const AUDIO_PLL: PllConstants = PllConstants::new(125, 3072, 8);
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// Set PLL0 to 24.576MHz, start, and wait for lock
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// This is not exposed by lpc55-hal, unfortunately. Copy their implementation here.
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||||
pub(crate) fn init_audio_pll() {
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let syscon = unsafe { &*pac::SYSCON::ptr() };
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let pmc = unsafe { &*pac::PMC::ptr() };
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let anactrl = unsafe { &*pac::ANACTRL::ptr() };
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||||
|
||||
debug!("start clk_in");
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pmc.pdruncfg0
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.modify(|_, w| w.pden_xtal32m().poweredon().pden_ldoxo32m().poweredon());
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||||
syscon.clock_ctrl.modify(|_, w| w.clkin_ena().enable());
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||||
anactrl
|
||||
.xo32m_ctrl
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||||
.modify(|_, w| w.enable_system_clk_out().enable());
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||||
|
||||
debug!("init pll0: {}", AUDIO_PLL);
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||||
pmc.pdruncfg0
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||||
.modify(|_, w| w.pden_pll0().poweredoff().pden_pll0_sscg().poweredoff());
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||||
syscon.pll0clksel.write(|w| w.sel().enum_0x1()); // clk_in
|
||||
syscon.pll0ctrl.write(|w| unsafe {
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||||
w.clken()
|
||||
.enable()
|
||||
.seli()
|
||||
.bits(AUDIO_PLL.seli)
|
||||
.selp()
|
||||
.bits(AUDIO_PLL.selp)
|
||||
});
|
||||
|
||||
syscon
|
||||
.pll0ndec
|
||||
.write(|w| unsafe { w.ndiv().bits(AUDIO_PLL.n) });
|
||||
syscon.pll0ndec.write(|w| unsafe {
|
||||
w.ndiv().bits(AUDIO_PLL.n).nreq().set_bit() // latch
|
||||
});
|
||||
|
||||
syscon
|
||||
.pll0pdec
|
||||
.write(|w| unsafe { w.pdiv().bits(AUDIO_PLL.p) });
|
||||
syscon.pll0pdec.write(|w| unsafe {
|
||||
w.pdiv().bits(AUDIO_PLL.p).preq().set_bit() // latch
|
||||
});
|
||||
|
||||
syscon.pll0sscg0.write(|w| unsafe { w.md_lbs().bits(0) });
|
||||
|
||||
syscon
|
||||
.pll0sscg1
|
||||
.write(|w| unsafe { w.mdiv_ext().bits(AUDIO_PLL.m).sel_ext().set_bit() });
|
||||
syscon.pll0sscg1.write(|w| unsafe {
|
||||
w.mdiv_ext()
|
||||
.bits(AUDIO_PLL.m)
|
||||
.sel_ext()
|
||||
.set_bit()
|
||||
.mreq()
|
||||
.set_bit() // latch
|
||||
.md_req()
|
||||
.set_bit() // latch
|
||||
});
|
||||
|
||||
pmc.pdruncfg0
|
||||
.modify(|_, w| w.pden_pll0().poweredon().pden_pll0_sscg().poweredon());
|
||||
info!("pll0 wait for lock");
|
||||
let mut i = 0usize;
|
||||
while syscon.pll0stat.read().lock().bit_is_clear() {
|
||||
i += 1;
|
||||
}
|
||||
info!("pll0 locked after {} loops", i);
|
||||
}
|
||||
|
||||
+46
-5
@@ -57,6 +57,11 @@ pub mod dac {
|
||||
mod noop;
|
||||
pub use self::noop::NoopDac as DacImpl;
|
||||
}
|
||||
#[cfg(feature = "wm8904")]
|
||||
pub mod dac {
|
||||
mod wm8904;
|
||||
pub use self::wm8904::Wm8904Dac as DacImpl;
|
||||
}
|
||||
|
||||
mod dma;
|
||||
#[cfg(feature = "hid")]
|
||||
@@ -76,7 +81,11 @@ const USB_FRAME_RATE: u32 = 8000; // microframe rate: 8000 for HS, 1000 for FS
|
||||
const QUEUE_RUNNING_UP: usize = ((FRAMES_PER_SLOT * N_SLOTS) * 4) / 10; // 40%
|
||||
const QUEUE_RUNNING_DOWN: usize = ((FRAMES_PER_SLOT * N_SLOTS) * 2) / 10; // 20%
|
||||
const NODATA_TIMEOUT_FRAMES: usize = SAMPLE_RATE as usize / 100; // ~100ms
|
||||
#[cfg(not(feature = "evk"))]
|
||||
const MCLK_FREQ: u32 = 24576000;
|
||||
#[cfg(feature = "evk")]
|
||||
const MCLK_FREQ: u32 = 24576000 / 2;
|
||||
|
||||
const SAMPLE_RATE: u32 = 192000;
|
||||
const HID_INTERVAL_MS: u8 = 100;
|
||||
|
||||
@@ -611,11 +620,6 @@ pub fn init_i2s(mut fc7: pac::FLEXCOMM7, i2s7: pac::I2S7, syscon: &mut Syscon) -
|
||||
.od()
|
||||
.normal()
|
||||
});
|
||||
pac::SYSCON::ptr()
|
||||
.as_ref()
|
||||
.unwrap()
|
||||
.mclkio
|
||||
.modify(|_, w| w.mclkio().input());
|
||||
pac::SYSCON::ptr()
|
||||
.as_ref()
|
||||
.unwrap()
|
||||
@@ -623,6 +627,33 @@ pub fn init_i2s(mut fc7: pac::FLEXCOMM7, i2s7: pac::I2S7, syscon: &mut Syscon) -
|
||||
.modify(|_, w| w.sel().enum_0x5()); // MCLK
|
||||
};
|
||||
|
||||
#[cfg(not(feature = "evk"))]
|
||||
unsafe {
|
||||
pac::SYSCON::ptr()
|
||||
.as_ref()
|
||||
.unwrap()
|
||||
.mclkio
|
||||
.modify(|_, w| w.mclkio().input());
|
||||
}
|
||||
#[cfg(feature = "evk")]
|
||||
unsafe {
|
||||
pac::SYSCON::ptr()
|
||||
.as_ref()
|
||||
.unwrap()
|
||||
.mclkclksel
|
||||
.modify(|_, w| w.sel().enum_0x1()); // PLL0
|
||||
pac::SYSCON::ptr()
|
||||
.as_ref()
|
||||
.unwrap()
|
||||
.mclkdiv
|
||||
.modify(|_, w| w.div().bits(1).halt().run().reset().released()); // div by 2 = PLL0 fout / 2 = 12.288MHz, max for WM8904 @ 96k
|
||||
pac::SYSCON::ptr()
|
||||
.as_ref()
|
||||
.unwrap()
|
||||
.mclkio
|
||||
.modify(|_, w| w.mclkio().output());
|
||||
}
|
||||
|
||||
// Select I2S TX function
|
||||
fc7.pselid.write(|w| w.persel().i2s_transmit());
|
||||
|
||||
@@ -646,10 +677,17 @@ fn main() -> ! {
|
||||
let usb0_vbus_pin = pins::Pio0_22::take()
|
||||
.unwrap()
|
||||
.into_usb0_vbus_pin(&mut iocon);
|
||||
|
||||
#[cfg(not(feature = "evk"))]
|
||||
let codec_i2c_pins = (
|
||||
pins::Pio0_16::take().unwrap().into_i2c4_scl_pin(&mut iocon),
|
||||
pins::Pio0_5::take().unwrap().into_i2c4_sda_pin(&mut iocon),
|
||||
);
|
||||
#[cfg(feature = "evk")]
|
||||
let codec_i2c_pins = (
|
||||
pins::Pio1_20::take().unwrap().into_i2c4_scl_pin(&mut iocon),
|
||||
pins::Pio1_21::take().unwrap().into_i2c4_sda_pin(&mut iocon),
|
||||
);
|
||||
let codec_i2s_pins = (
|
||||
pins::Pio0_21::take().unwrap().into_spi7_sck_pin(&mut iocon),
|
||||
pins::Pio0_20::take().unwrap().into_i2s7_sda_pin(&mut iocon),
|
||||
@@ -691,6 +729,9 @@ fn main() -> ! {
|
||||
.configure(&mut anactrl, &mut pmc, &mut syscon)
|
||||
.unwrap();
|
||||
hw::init_sys_pll1();
|
||||
#[cfg(feature = "evk")]
|
||||
hw::init_audio_pll();
|
||||
|
||||
let mut delay_timer = Timer::new(
|
||||
hal.ctimer
|
||||
.0
|
||||
|
||||
Reference in New Issue
Block a user