add txerr handler (probably)

firmware/src/main.rs

@@ -200,6 +200,15 @@ fn DMA0() {
     }
 }
 
+#[interrupt]
+fn FLEXCOMM7() {
+    // Count I2S TX FIFO error (should be underrun, assuming we set up our DMA trigger correctly)
+    PERF.audio_underflows.fetch_add(1, Ordering::Relaxed);
+    unsafe { &*pac::I2S7::ptr() }
+        .fifostat
+        .modify(|_, w| w.txerr().set_bit())
+}
+
 #[repr(u8)]
 #[derive(Clone, Copy, NoUninit, Eq, PartialEq)]
 enum AudioState {
@@ -351,11 +360,15 @@ impl<D: Dac<I>, I> Audio<'_, D, I> {
                 .datapause()
                 .normal()
         });
+
+        unsafe { pac::NVIC::unmask(pac::Interrupt::FLEXCOMM7) };
         self.dac.init();
     }
     ///Transition -> Stopped:
     ///clear queue, mute DAC, mask I2S ISR, stop I2S peripheral, disable & reset feedback and performance queues
     fn stop(&mut self) {
+        // Disable FIFO error interrupt
+        self.i2s.i2s.fifointenclr.write(|w| w.txerr().set_bit());
         dma_ring().stop();
         pac::NVIC::mask(pac::Interrupt::DMA0);
         self.dac.mute();
@@ -399,6 +412,10 @@ impl<D: Dac<I>, I> Audio<'_, D, I> {
             .fifocfg
             .modify(|_, w| w.enabletx().enabled().dmatx().enabled());
         dma_ring().run();
+        // clear tx error status
+        self.i2s.i2s.fifostat.write(|w| w.txerr().set_bit());
+        // enable tx error interrupt
+        self.i2s.i2s.fifointenset.write(|w| w.txerr().enabled());
         unsafe {
             pac::NVIC::unmask(pac::Interrupt::DMA0);
         }